Subversion Repositories ps3ware

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Ignore whitespace Rev 204 → Rev 205

/trunk/libps3rsx/src/geometry/geometry.h
8,6 → 8,7
typedef enum
{
TRIANGLES = 0x5,
QUADS = 0x8,
}
primitives_t;
 
15,8 → 16,10
{
EMPTY=0x0,//not used?
FLOAT=0x2,
HALF = 0x3,
UBYTE=0x4,
SHORT=0x5
SHORT=0x5,
 
}
geom_format_t;
 
91,8 → 94,9
);
 
 
int draw_indexed_primitives
int draw_primitives
(
uint32_t use_index_buffer,
primitives_t type,
uint32_t first_index,
uint32_t num_primitives,
/trunk/libps3rsx/src/geometry/geometry.c
97,8 → 97,11
}
 
 
int draw_indexed_primitives
 
 
int draw_primitives
(
uint32_t use_index_buffer,
primitives_t type,
uint32_t first,
uint32_t num_primitives,
115,6 → 118,9
return 0;
}
uint32_t vdata = use_index_buffer ? NV40TCL_INDEX_DATA : NV40TCL_VB_VERTEX_BATCH;
vdata |= 0x40000000;
BEGIN_RING(Nv3D, NV40TCL_BEGIN_END, 1);
OUT_RING (type);
 
122,7 → 128,7
 
if( end == 0 )
{
BEGIN_RING(Nv3D, NV40TCL_INDEX_DATA | 0x40000000, num_primitives / 0x100 );
BEGIN_RING(Nv3D, vdata, num_primitives / 0x100 );
for( i = 0; i < num_primitives; i += 0x100 )
{
OUT_RING( ( first << NV40TCL_VB_VERTEX_BATCH_START_SHIFT ) | ( 0xff << NV40TCL_VB_VERTEX_BATCH_COUNT_SHIFT ) );
131,7 → 137,7
}
else
{
BEGIN_RING(Nv3D, NV40TCL_INDEX_DATA | 0x40000000, 1 + num_primitives / 0x100 );
BEGIN_RING(Nv3D, vdata, 1 + num_primitives / 0x100 );
for( i = 0; i < num_primitives - end; i += 0x100 )
{
OUT_RING( ( first << NV40TCL_VB_VERTEX_BATCH_START_SHIFT ) | ( 0xff << NV40TCL_VB_VERTEX_BATCH_COUNT_SHIFT ) );
150,3 → 156,5
return ptr - fifo;
}
 
 
 
/trunk/libps3rsx/src/rop/rop.c
New file
0,0 → 1,100
/*
* PS3 GPU blitting test program
*
* Copyright 2007 Vivien Chappelier <vivien.chappelier@free.fr>
* Copyright 2007 Peter Popov <IronSPeter@gmail.com>
*
*/
#include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
#include <unistd.h>
#include <string.h>
#include <sys/mman.h>
#include <sys/ioctl.h>
#include <signal.h>
#include <fcntl.h>
 
#include "../../include/nouveau_class.h"
#include "../fifo/utils.h"
#include "rop.h"
 
int set_blend_mode
(
const blend_desc_t *desc,
uint32_t *fifo,
uint32_t hw_sub
)
{
uint32_t *ptr = fifo;
uint32_t Nv3D = hw_sub;
 
size_t dst = desc->src_color_blend | ( (size_t)desc->src_alpha_blend << 16 );
size_t src = desc->dst_color_blend | ( (size_t)desc->dst_alpha_blend << 16 );
BEGIN_RING( Nv3D, NV40TCL_BLEND_FUNC_SRC, 2 );
OUT_RING( src );
OUT_RING( dst );
BEGIN_RING( Nv3D, NV40TCL_BLEND_EQUATION, 1 );
OUT_RING( 0x80068006 );
return ptr - fifo;
}
 
int blend_enable
(
uint32_t blend_enable,
uint32_t *fifo,
uint32_t hw_sub
)
{
uint32_t *ptr = fifo;
uint32_t Nv3D = hw_sub;
 
BEGIN_RING( Nv3D, NV40TCL_BLEND_ENABLE, 1 );
OUT_RING( blend_enable );
return ptr - fifo;
 
}
 
int set_depth_mode
(
depth_modes_t mode,
uint32_t *fifo,
uint32_t hw_sub
)
{
uint32_t *ptr = fifo;
uint32_t Nv3D = hw_sub;
 
BEGIN_RING( Nv3D, NV40TCL_DEPTH_FUNC, 1 );
OUT_RING( mode );
return ptr - fifo;
 
}
 
 
int depth_enable
(
uint32_t depth_write_enable,
uint32_t depth_test_enable,
uint32_t *fifo,
uint32_t hw_sub
)
{
uint32_t *ptr = fifo;
uint32_t Nv3D = hw_sub;
 
BEGIN_RING( Nv3D, NV40TCL_DEPTH_WRITE_ENABLE, 2 );
OUT_RING( depth_write_enable );
OUT_RING( depth_test_enable );
return ptr - fifo;
 
}
/trunk/libps3rsx/src/rop/rop.h
New file
0,0 → 1,79
/*
* PS3 GPU blitting test program
*
* Copyright 2007 Peter Popov <IronSPeter@gmail.com>
*
*/
 
 
typedef enum
{
ZERO = 0x0,
ONE = 0x1,
SRC_COLOR = 0x300,
INV_SRC_COLOR = 0x301,
SRC_ALPHA = 0x302,
INV_SRC_ALPHA = 0x0303,
DST_ALPHA = 0x304,
INV_DST_ALPHA = 0x0305,
DST_COLOR = 0x306,
INV_DST_COLOR = 0x307,
SRC_ALPHA_SAT = 0x308,
CONST_COLOR = 0x8001,
INV_CONST_COLOR = 0x8002,
CONST_ALPHA = 0x8003,
INV_CONST_ALPHA = 0x8004,
} blend_modes_t;
 
typedef enum
{
DEPTH_FUNC_NEVER = 0x200,
DEPTH_FUNC_LESS = 0x201,
DEPTH_FUNC_EQUAL = 0x202,
DEPTH_FUNC_LEQUAL = 0x203,
DEPTH_FUNC_GREATER = 0x204,
DEPTH_FUNC_NOTEQUAL = 0x205,
DEPTH_FUNC_GEQUAL = 0x206,
DEPTH_FUNC_ALWAYS = 0x207,
} depth_modes_t;
 
typedef struct
{
blend_modes_t src_color_blend;
blend_modes_t src_alpha_blend;
blend_modes_t dst_color_blend;
blend_modes_t dst_alpha_blend;
} blend_desc_t;
 
int set_blend_mode
(
const blend_desc_t *desc,
uint32_t *fifo_buffer,
uint32_t hw_sub
);
 
 
int blend_enable
(
uint32_t blend_enable,
uint32_t *fifo_buffer,
uint32_t hw_sub
);
 
 
int set_depth_mode
(
depth_modes_t mode,
uint32_t *fifo_buffer,
uint32_t hw_sub
);
 
int depth_enable
(
uint32_t depth_write_enable,
uint32_t depth_test_enable,
uint32_t *fifo_buffer,
uint32_t hw_sub
);
/trunk/libps3rsx/src/fifo/utils.c
83,7 → 83,7
BEGIN_RING(Nv3D, NV40TCL_STENCIL_BACK_ENABLE, 1);
OUT_RING (0);
BEGIN_RING(Nv3D, NV40TCL_ALPHA_TEST_ENABLE, 1);
OUT_RING (1);
OUT_RING (0);
BEGIN_RING(Nv3D, NV40TCL_ALPHA_TEST_FUNC, 1);
OUT_RING (NV40TCL_ALPHA_TEST_FUNC_GREATER);
309,6 → 309,69
}
 
 
void analyze_fifo( uint32_t *fifo, int length )
{
uint32_t jmps = 0;
uint32_t nops = 0;
uint32_t ring = 0;
uint32_t cmds = 0;
uint32_t regs = 0;
uint32_t seqs = 0;
uint32_t incr = 0;
uint32_t *ptr = fifo;
while( 1 )
{
uint32_t cmd = *ptr;
if( ( cmd & 0x20000000 ) && ( ring == 0 ) )
{
++jmps;
}
else if( cmd == 0 && ( ring == 0 ) )
{
++nops;
}
else if( ring != 0 )
{
--ring;
if( incr )
{
++regs;
}
}
else if( ring == 0 )
{
uint32_t nring = ( cmd >> 18 ) & 0xffff;
uint32_t nincr = cmd & 0x40000000;
uint32_t nregs = cmd & ( ( 1 << 13 ) - 1 );
if( incr && nincr && regs == nregs )
{
++seqs;
}
regs = nregs;
incr = nincr;
ring = nring;
printf( "%d %d %x %d\n", incr, ring, regs, ( cmd >> 13 ) & 15 );
++cmds;
}
++ptr;
if( ptr >= fifo + length )
{
break;
}
}
printf( "jmps : %d \n", jmps );
printf( "nops : %d \n", nops );
printf( "cmds : %d \n", cmds );
printf( "seqs : %d \n", seqs );
}
 
int flip_scrn(struct gpu *gpu, int off)
{
int val = ioctl(gpu->rsx_fd, PS3RSX_IOCTL_FLIP_SCRN, off );
/trunk/libps3rsx/src/fifo/utils.h
97,8 → 97,8
int setup_buffers( const setup_buffer_t *buffers, uint32_t *fifo, uint32_t hw_sub );
 
 
void analyze_fifo( uint32_t *fifo, int length );
 
 
void fifo_push(struct gpu *gpu, int len);
void fifo_wait(struct gpu *gpu);
int sync_gpu(struct gpu *gpu );