<html><head><meta name="color-scheme" content="light dark"></head><body><pre style="word-wrap: break-word; white-space: pre-wrap;">diff -burN binutils-2.16.1/bfd/archures.c binutils-psp/bfd/archures.c
--- binutils-2.16.1/bfd/archures.c	2005-01-17 14:08:03.000000000 +0000
+++ binutils-psp/bfd/archures.c	2006-05-09 02:55:36.000000000 +0100
@@ -155,6 +155,7 @@
 .#define bfd_mach_mips16		16
 .#define bfd_mach_mips5                 5
 .#define bfd_mach_mips_sb1              12310201 {* octal 'SB', 01 *}
+.#define bfd_mach_mips_allegrex         10111431 {* octal 'AL', 31 *}
 .#define bfd_mach_mipsisa32             32
 .#define bfd_mach_mipsisa32r2           33
 .#define bfd_mach_mipsisa64             64
diff -burN binutils-2.16.1/bfd/bfd-in2.h binutils-psp/bfd/bfd-in2.h
--- binutils-2.16.1/bfd/bfd-in2.h	2005-03-02 21:23:20.000000000 +0000
+++ binutils-psp/bfd/bfd-in2.h	2006-05-09 02:55:36.000000000 +0100
@@ -1600,6 +1600,7 @@
 #define bfd_mach_mips16                16
 #define bfd_mach_mips5                 5
 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
+#define bfd_mach_mips_allegrex         10111431 /* octal 'AL', 31 */
 #define bfd_mach_mipsisa32             32
 #define bfd_mach_mipsisa32r2           33
 #define bfd_mach_mipsisa64             64
diff -burN binutils-2.16.1/bfd/cpu-mips.c binutils-psp/bfd/cpu-mips.c
--- binutils-2.16.1/bfd/cpu-mips.c	2005-03-03 11:40:58.000000000 +0000
+++ binutils-psp/bfd/cpu-mips.c	2006-05-09 02:55:36.000000000 +0100
@@ -86,6 +86,7 @@
   I_mipsisa64,
   I_mipsisa64r2,
   I_sb1,
+  I_allegrex,
 };
 
 #define NN(index) (&amp;arch_info_struct[(index) + 1])
@@ -118,7 +119,8 @@
   N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
   N (64, 64, bfd_mach_mipsisa64,  "mips:isa64",   FALSE, NN(I_mipsisa64)),
   N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
-  N (64, 64, bfd_mach_mips_sb1, "mips:sb1",       FALSE, 0),
+  N (64, 64, bfd_mach_mips_sb1, "mips:sb1",       FALSE, NN(I_sb1)),
+  N (32, 32, bfd_mach_mips_allegrex, "mips:allegrex", FALSE, 0),
 };
 
 /* The default architecture is mips:3000, but with a machine number of
diff -burN binutils-2.16.1/bfd/elfxx-mips.c binutils-psp/bfd/elfxx-mips.c
--- binutils-2.16.1/bfd/elfxx-mips.c	2005-05-28 22:58:29.000000000 +0100
+++ binutils-psp/bfd/elfxx-mips.c	2006-05-09 02:55:36.000000000 +0100
@@ -4669,6 +4669,9 @@
     case E_MIPS_MACH_SB1:
       return bfd_mach_mips_sb1;
 
+    case E_MIPS_MACH_ALLEGREX:
+      return bfd_mach_mips_allegrex;
+
     default:
       switch (flags &amp; EF_MIPS_ARCH)
 	{
@@ -7941,6 +7944,10 @@
       val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
       break;
 
+    case bfd_mach_mips_allegrex:
+      val = E_MIPS_ARCH_2 | E_MIPS_MACH_ALLEGREX;
+      break;
+
     case bfd_mach_mipsisa32:
       val = E_MIPS_ARCH_32;
       break;
@@ -8422,6 +8429,8 @@
   if (dynobj != NULL &amp;&amp; force_local &amp;&amp; h-&gt;root.type != STT_TLS)
     {
       got = mips_elf_got_section (dynobj, FALSE);
+      if (got)
+        {
       g = mips_elf_section_data (got)-&gt;u.got_info;
 
       if (g-&gt;next)
@@ -8472,6 +8481,7 @@
 	  g-&gt;global_gotno--;
 	}
     }
+   }
 
   _bfd_elf_link_hash_hide_symbol (info, &amp;h-&gt;root, force_local);
 }
@@ -9641,6 +9651,7 @@
   /* MIPS II extensions.  */
   { bfd_mach_mips4000, bfd_mach_mips6000 },
   { bfd_mach_mipsisa32, bfd_mach_mips6000 },
+  { bfd_mach_mips_allegrex, bfd_mach_mips6000 },
 
   /* MIPS I extensions.  */
   { bfd_mach_mips6000, bfd_mach_mips3000 },
diff -burN binutils-2.16.1/bfd/Makefile.am binutils-psp/bfd/Makefile.am
--- binutils-2.16.1/bfd/Makefile.am	2005-06-12 19:58:52.000000000 +0100
+++ binutils-psp/bfd/Makefile.am	2006-05-09 02:55:36.000000000 +0100
@@ -3,7 +3,7 @@
 AUTOMAKE_OPTIONS = 1.9 cygnus
 
 # Uncomment the following line when doing a release.
-RELEASE=y
+#RELEASE=y
 
 INCDIR = $(srcdir)/../include
 CSEARCH = -I. -I$(srcdir) -I$(INCDIR)
diff -burN binutils-2.16.1/bfd/Makefile.in binutils-psp/bfd/Makefile.in
--- binutils-2.16.1/bfd/Makefile.in	2005-06-12 19:58:55.000000000 +0100
+++ binutils-psp/bfd/Makefile.in	2006-05-09 02:55:36.000000000 +0100
@@ -250,7 +250,7 @@
 AUTOMAKE_OPTIONS = 1.9 cygnus
 
 # Uncomment the following line when doing a release.
-RELEASE=y
+#RELEASE=y
 INCDIR = $(srcdir)/../include
 CSEARCH = -I. -I$(srcdir) -I$(INCDIR)
 MKDEP = gcc -MM
diff -burN binutils-2.16.1/bfd/version.h binutils-psp/bfd/version.h
--- binutils-2.16.1/bfd/version.h	2005-06-12 18:37:59.000000000 +0100
+++ binutils-psp/bfd/version.h	2006-05-09 02:55:36.000000000 +0100
@@ -1,3 +1,3 @@
-#define BFD_VERSION_DATE 20050612
+#define BFD_VERSION_DATE (PSPDEV 20060116)
 #define BFD_VERSION @bfd_version@
 #define BFD_VERSION_STRING @bfd_version_string@
diff -burN binutils-2.16.1/binutils/readelf.c binutils-psp/binutils/readelf.c
--- binutils-2.16.1/binutils/readelf.c	2005-04-20 19:43:36.000000000 +0100
+++ binutils-psp/binutils/readelf.c	2006-05-09 02:55:36.000000000 +0100
@@ -2043,6 +2043,7 @@
 	    case E_MIPS_MACH_5500: strcat (buf, ", 5500"); break;
 	    case E_MIPS_MACH_SB1:  strcat (buf, ", sb1");  break;
 	    case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break;
+	    case E_MIPS_MACH_ALLEGREX: strcat (buf, ", allegrex"); break;
 	    case 0:
 	    /* We simply ignore the field in this case to avoid confusion:
 	       MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
diff -burN binutils-2.16.1/config.sub binutils-psp/config.sub
--- binutils-2.16.1/config.sub	2005-01-19 00:34:56.000000000 +0000
+++ binutils-psp/config.sub	2006-05-09 02:55:36.000000000 +0100
@@ -253,6 +253,7 @@
 	| mipsisa64sb1 | mipsisa64sb1el \
 	| mipsisa64sr71k | mipsisa64sr71kel \
 	| mipstx39 | mipstx39el \
+	| mipsallegrex | mipsallegrexel \
 	| mn10200 | mn10300 \
 	| msp430 \
 	| ns16k | ns32k \
@@ -326,6 +327,7 @@
 	| mipsisa64sb1-* | mipsisa64sb1el-* \
 	| mipsisa64sr71k-* | mipsisa64sr71kel-* \
 	| mipstx39-* | mipstx39el-* \
+	| mipsallegrex-* | mipsallegrexel-* \
 	| mmix-* \
 	| msp430-* \
 	| none-* | np1-* | ns16k-* | ns32k-* \
@@ -665,6 +667,10 @@
 		basic_machine=m68k-atari
 		os=-mint
 		;;
+	psp)
+		basic_machine=mipsallegrexel-psp
+		os=-elf
+		;;
 	mips3*-*)
 		basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
 		;;
diff -burN binutils-2.16.1/configure binutils-psp/configure
--- binutils-2.16.1/configure	2005-02-28 14:06:59.000000000 +0000
+++ binutils-psp/configure	2006-05-09 02:55:10.000000000 +0100
@@ -1034,7 +1034,7 @@
 
 # Some tools are only suitable for building in a "native" situation.
 # Remove these if host!=target.  
-native_only="autoconf automake libtool fileutils find gawk gettext gzip hello indent m4 rcs recode sed shellutils tar textutils uudecode wdiff gprof target-groff guile perl time ash bash bzip2 prms gnuserv target-gperf"
+native_only="autoconf automake libtool fileutils find gawk gettext gzip hello indent m4 rcs recode sed shellutils tar textutils uudecode wdiff target-groff guile perl time ash bash bzip2 prms gnuserv target-gperf"
 
 # Similarly, some are only suitable for cross toolchains.
 # Remove these if host=target.
@@ -1516,7 +1516,7 @@
     noconfigdirs="$noconfigdirs target-newlib target-libgloss"
     ;;
   mips*-*-*)
-    noconfigdirs="$noconfigdirs gprof ${libgcj}"
+    noconfigdirs="$noconfigdirs ${libgcj}"
     ;;
   romp-*-*)
     noconfigdirs="$noconfigdirs bfd binutils ld gas opcodes target-libgloss ${libgcj}"
diff -burN binutils-2.16.1/gas/config/tc-mips.c binutils-psp/gas/config/tc-mips.c
--- binutils-2.16.1/gas/config/tc-mips.c	2005-06-12 19:07:03.000000000 +0100
+++ binutils-psp/gas/config/tc-mips.c	2006-05-09 02:55:36.000000000 +0100
@@ -92,6 +92,32 @@
 
 #define ZERO 0
 #define AT  1
+#define V0  2
+#define V1  3
+#define A0  4
+#define A1  5
+#define A2  6
+#define A3  7
+#define T0  8
+#define T1  9
+#define T2  10
+#define T3  11
+#define T4  12
+#define T5  13
+#define T6  14
+#define T7  15
+#define S0  16
+#define S1  17
+#define S2  18
+#define S3  19
+#define S4  20
+#define S5  21
+#define S6  22
+#define S7  23
+#define T8  24
+#define T9  25
+#define K0  26
+#define K1  27
 #define TREG 24
 #define PIC_CALL_REG 25
 #define KT0 26
@@ -365,11 +391,15 @@
 #define CPU_HAS_MDMX(cpu)	(FALSE                 \
 				 )
 
+/* True if the given CPU belongs to the Allegrex family.  */
+#define CPU_IS_ALLEGREX(CPU)	((CPU) == CPU_ALLEGREX	\
+    				 )
+
 /* True if CPU has a dror instruction.  */
 #define CPU_HAS_DROR(CPU)	((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
 
 /* True if CPU has a ror instruction.  */
-#define CPU_HAS_ROR(CPU)	CPU_HAS_DROR (CPU)
+#define CPU_HAS_ROR(CPU)	CPU_HAS_DROR (CPU) || CPU_IS_ALLEGREX (CPU)
 
 /* True if mflo and mfhi can be immediately followed by instructions
    which write to the HI and LO registers.
@@ -393,6 +423,7 @@
    || mips_opts.arch == CPU_R12000                    \
    || mips_opts.arch == CPU_RM7000                    \
    || mips_opts.arch == CPU_VR5500                    \
+   || mips_opts.arch == CPU_ALLEGREX                  \
    )
 
 /* Whether the processor uses hardware interlocks to protect reads
@@ -1142,6 +1173,8 @@
 static expressionS imm_expr;
 static expressionS imm2_expr;
 static expressionS offset_expr;
+static expressionS vimm_expr[4];
+static expressionS voffset_expr[4];
 
 /* Relocs associated with imm_expr and offset_expr.  */
 
@@ -1150,6 +1183,15 @@
 static bfd_reloc_code_real_type offset_reloc[3]
   = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
 
+/* set by vfpu code for prefix instructions */
+
+static bfd_boolean vfpu_dprefix;
+static char vfpu_dprefix_str[64];
+static bfd_boolean vfpu_sprefix;
+static char vfpu_sprefix_str[64];
+static bfd_boolean vfpu_tprefix;
+static char vfpu_tprefix_str[64];
+
 /* These are set by mips16_ip if an explicit extension is used.  */
 
 static bfd_boolean mips16_small, mips16_ext;
@@ -1641,6 +1683,62 @@
       return;
     }
 
+  /* If we've generated operands for a VFPU prefix instruction then we need
+     to assemble and append the prefix instruction before emitting the
+     instruction it prefixes.  Note that in mips_ip prefix operands do not
+     cause any side effects with imm_expr or offset_expr.  If they did
+     we'd have to save and restore them here.  */
+  if (CPU_IS_ALLEGREX (mips_opts.arch) &amp;&amp; ((vfpu_dprefix || vfpu_sprefix || vfpu_tprefix)))
+    {
+
+      if (mips_opts.noreorder
+	  &amp;&amp; ( history[0].insn_mo-&gt;pinfo &amp; (INSN_UNCOND_BRANCH_DELAY
+					   | INSN_COND_BRANCH_DELAY
+					   | INSN_COND_BRANCH_LIKELY)))
+	{
+	  as_bad (_("instruction with prefix cannot be used in branch delay slot"));
+	}
+
+      if (vfpu_dprefix)
+	{
+	  struct mips_cl_insn prefix;
+	  bfd_reloc_code_real_type unused_reloc[3]
+	    = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
+	  char buf[256];
+
+	  sprintf (buf, "vpfxd %s", vfpu_dprefix_str);
+	  mips_ip (buf, &amp;prefix);
+	  append_insn (&amp;prefix, NULL, unused_reloc);
+	  vfpu_dprefix = FALSE;
+	}
+
+      if (vfpu_sprefix)
+	{
+	  struct mips_cl_insn prefix;
+	  bfd_reloc_code_real_type unused_reloc[3]
+	    = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
+	  char buf[256];
+
+	  sprintf (buf, "vpfxs %s", vfpu_sprefix_str);
+	  mips_ip (buf, &amp;prefix);
+	  append_insn ( &amp;prefix, NULL, unused_reloc);
+	  vfpu_sprefix = FALSE;
+	}
+      
+      if (vfpu_tprefix)
+	{
+	  struct mips_cl_insn prefix;
+	  bfd_reloc_code_real_type unused_reloc[3]
+	    = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
+	  char buf[256];
+
+	  sprintf (buf, "vpfxt %s", vfpu_tprefix_str);
+	  mips_ip (buf, &amp;prefix);
+	  append_insn (&amp;prefix, NULL, unused_reloc);
+	  vfpu_tprefix = FALSE;
+	}
+    }
+
   if (insn.insn_mo-&gt;pinfo == INSN_MACRO)
     {
       macro_start ();
@@ -3128,6 +3226,55 @@
 	  insn.insn_opcode |= va_arg (args, unsigned long);
 	  continue;
 
+	/* VFPU fields */
+	case '?':
+	  switch (*fmt++)
+	    {
+	    case 'o':
+	      *r = (bfd_reloc_code_real_type) va_arg (args, int);
+	      assert (*r == BFD_RELOC_GPREL16
+		      || *r == BFD_RELOC_MIPS_LITERAL
+		      || *r == BFD_RELOC_MIPS_HIGHER
+		      || *r == BFD_RELOC_HI16_S
+		      || *r == BFD_RELOC_LO16
+		      || *r == BFD_RELOC_MIPS_GOT16
+		      || *r == BFD_RELOC_MIPS_CALL16
+		      || *r == BFD_RELOC_MIPS_GOT_DISP
+		      || *r == BFD_RELOC_MIPS_GOT_PAGE
+		      || *r == BFD_RELOC_MIPS_GOT_OFST
+		      || *r == BFD_RELOC_MIPS_GOT_LO16
+		      || *r == BFD_RELOC_MIPS_CALL_LO16);
+	      break;
+	    case 'd':
+	      insn.insn_opcode |= va_arg (args, int) &lt;&lt; VF_SH_VD;
+	      fmt += 2;
+	      break;
+	    case 's':
+	      insn.insn_opcode |= va_arg (args, int) &lt;&lt; VF_SH_VS;
+	      fmt += 2;
+	      break;
+	    case 'm':
+	      {
+		int vtreg = va_arg (args, int);
+		insn.insn_opcode |= (vtreg &amp; VF_MASK_VML) &lt;&lt; VF_SH_VML;
+		insn.insn_opcode |= ((vtreg &gt;&gt; 5) &amp; VF_MASK_VMH) &lt;&lt; VF_SH_VMH;
+		fmt += 2;
+	      }
+	      break;
+	    case 'n':
+	      {
+		int vtreg = va_arg (args, int);
+		insn.insn_opcode |= (vtreg &amp; VF_MASK_VNL) &lt;&lt; VF_SH_VNL;
+		insn.insn_opcode |= ((vtreg &gt;&gt; 5) &amp; VF_MASK_VNH) &lt;&lt; VF_SH_VNH;
+		fmt += 2;
+	      }
+	      break;
+	    case 'e':
+	      insn.insn_opcode |= va_arg (args, int) &lt;&lt; VF_SH_MCOND;
+	      break;
+	    }
+	  continue;
+
 	default:
 	  internalError ();
 	}
@@ -4103,6 +4250,7 @@
 macro (struct mips_cl_insn *ip)
 {
   register int treg, sreg, dreg, breg;
+  int vsreg, vtreg, vdreg, vmreg, vwb;
   int tempreg;
   int mask;
   int used_at = 0;
@@ -4128,6 +4276,13 @@
   sreg = breg = (ip-&gt;insn_opcode &gt;&gt; 21) &amp; 0x1f;
   mask = ip-&gt;insn_mo-&gt;mask;
 
+  vmreg = ((ip-&gt;insn_opcode &gt;&gt; 16) &amp; 0x1f)
+	| ((ip-&gt;insn_opcode &lt;&lt;  5) &amp; 0x60);
+  vtreg = (ip-&gt;insn_opcode &gt;&gt; 16) &amp; 0x7f;
+  vsreg = (ip-&gt;insn_opcode &gt;&gt; 8) &amp; 0x7f;
+  vdreg = (ip-&gt;insn_opcode &gt;&gt; 0) &amp; 0x7f;
+  vwb = (ip-&gt;insn_opcode &gt;&gt; 1) &amp; 0x1;
+
   expr1.X_op = O_constant;
   expr1.X_op_symbol = NULL;
   expr1.X_add_symbol = NULL;
@@ -5654,6 +5809,26 @@
       /* Itbl support may require additional care here.  */
       coproc = 1;
       goto ld;
+    case M_LV_S_AB:
+      s = "lv.s";
+      /* Itbl support may require additional care here.  */
+      coproc = 1;
+      goto ld;
+    case M_LV_Q_AB:
+      s = "lv.q";
+      /* Itbl support may require additional care here.  */
+      coproc = 1;
+      goto ld;
+    case M_LVL_Q_AB:
+      s = "lvl.q";
+      /* Itbl support may require additional care here.  */
+      coproc = 1;
+      goto ld;
+    case M_LVR_Q_AB:
+      s = "lvr.q";
+      /* Itbl support may require additional care here.  */
+      coproc = 1;
+      goto ld;
     case M_LWL_AB:
       s = "lwl";
       lr = 1;
@@ -5738,6 +5913,29 @@
       /* Itbl support may require additional care here.  */
       coproc = 1;
       goto st;
+    case M_SV_S_AB:
+      s = "sv.s";
+      /* Itbl support may require additional care here.  */
+      coproc = 1;
+      goto st;
+    case M_SV_Q_AB:
+      if (vwb)
+	s = "vwb.q";
+      else
+	s = "sv.q";
+      /* Itbl support may require additional care here.  */
+      coproc = 1;
+      goto st;
+    case M_SVL_Q_AB:
+      s = "svl.q";
+      /* Itbl support may require additional care here.  */
+      coproc = 1;
+      goto st;
+    case M_SVR_Q_AB:
+      s = "svr.q";
+      /* Itbl support may require additional care here.  */
+      coproc = 1;
+      goto st;
     case M_SWL_AB:
       s = "swl";
       goto st;
@@ -5787,6 +5985,22 @@
 	  || mask == M_L_DAB
 	  || mask == M_S_DAB)
 	fmt = "T,o(b)";
+      else if (mask == M_LV_S_AB
+	       || mask == M_SV_S_AB)
+	{
+	  fmt = "?m0x,?o(b)";
+	  treg = vmreg;
+	}
+      else if (mask == M_LV_Q_AB
+	       || mask == M_SV_Q_AB
+	       || mask == M_LVL_Q_AB
+	       || mask == M_LVR_Q_AB
+	       || mask == M_SVL_Q_AB
+	       || mask == M_SVR_Q_AB)
+	{
+	  fmt = "?n3x,?o(b)";
+	  treg = vmreg;
+	}
       else if (coproc)
 	fmt = "E,o(b)";
       else
@@ -6150,6 +6364,138 @@
 	  break;
 	}
 
+    case M_LVI_S_SS:
+    case M_LVI_P_SS:
+    case M_LVI_T_SS:
+    case M_LVI_Q_SS:
+      {
+	int mtx = (vtreg &gt;&gt; VF_SH_MR_MTX) &amp; VF_MASK_MR_MTX;
+	int idx = (vtreg &gt;&gt; VF_SH_MR_IDX) &amp; VF_MASK_MR_IDX;
+	int fsl = 0;
+	int rxc = 0;
+	int vtreg_s = 0;
+	int vnum = 0;
+	int vat = 0;
+	int i;
+
+	switch (mask)
+	  {
+	  case M_LVI_S_SS:
+	    vnum = 1;
+	    fsl = (vtreg &gt;&gt; VF_SH_MR_FSL) &amp; VF_MASK_MR_FSL;
+	    rxc = 0;
+	    break;
+	  case M_LVI_P_SS:
+	    vnum = 2;
+	    fsl = ((vtreg &gt;&gt; VF_SH_MR_VFSL) &amp; VF_MASK_MR_VFSL) &lt;&lt; 1;
+	    rxc = (vtreg &gt;&gt; VF_SH_MR_RXC) &amp; VF_MASK_MR_RXC;
+	    break;
+	  case M_LVI_T_SS:
+	    vnum = 3;
+	    fsl = (vtreg &gt;&gt; VF_SH_MR_VFSL) &amp; VF_MASK_MR_VFSL;
+	    rxc = (vtreg &gt;&gt; VF_SH_MR_RXC) &amp; VF_MASK_MR_RXC;
+	    break;
+	  case M_LVI_Q_SS:
+	    vnum = 4;
+	    fsl = 0;
+	    rxc = (vtreg &gt;&gt; VF_SH_MR_RXC) &amp; VF_MASK_MR_RXC;
+	    break;
+	  }
+	if (rxc)
+	  vtreg_s = (mtx &lt;&lt; VF_SH_MR_MTX) | (idx &lt;&lt; VF_SH_MR_FSL)
+		  | (fsl &lt;&lt; VF_SH_MR_IDX);
+	else
+	  vtreg_s = (mtx &lt;&lt; VF_SH_MR_MTX) | (idx &lt;&lt; VF_SH_MR_IDX)
+		  | (fsl &lt;&lt; VF_SH_MR_FSL);
+
+	for (i = 0; i &lt; vnum; i++) {
+	  imm_expr = vimm_expr[i];
+	  offset_expr = voffset_expr[i];
+
+	  if (imm_expr.X_op == O_constant)
+	    {
+	      load_register (AT, &amp;imm_expr, 0);
+	      macro_build ((expressionS *) NULL,
+			   "mtv", "t,?d0z", AT, vtreg_s);
+	      vat = 1;
+	    }
+	  else
+	    {
+	      assert (offset_expr.X_op == O_symbol
+		      &amp;&amp; strcmp (segment_name (S_GET_SEGMENT
+					       (offset_expr.X_add_symbol)),
+				 ".lit4") == 0
+		      &amp;&amp; offset_expr.X_add_number == 0);
+	      macro_build (&amp;offset_expr,
+			   "lv.s", "?m0x,?o(b)", vtreg_s,
+			   (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
+	    }
+
+	  if (rxc)
+	    vtreg_s += (1 &lt;&lt; VF_SH_MR_IDX);
+	  else
+	    vtreg_s += (1 &lt;&lt; VF_SH_MR_FSL);
+	}
+
+	if (vat)
+	  break;
+	else
+	  return;
+      }
+
+    case M_LVHI_S_SS:
+    case M_LVHI_P_SS:
+      {
+	int mtx = (vtreg &gt;&gt; VF_SH_MR_MTX) &amp; VF_MASK_MR_MTX;
+	int idx = (vtreg &gt;&gt; VF_SH_MR_IDX) &amp; VF_MASK_MR_IDX;
+	int fsl = 0;
+	int rxc = 0;
+	int vtreg_s = 0;
+	int vnum = 0;
+	int i;
+	unsigned int f16v;
+	char f16v_str[16];
+
+	switch (mask)
+	  {
+	  case M_LVHI_S_SS:
+	    vnum = 2;
+	    fsl = (vtreg &gt;&gt; VF_SH_MR_FSL) &amp; VF_MASK_MR_FSL;
+	    rxc = 0;
+	    break;
+	  case M_LVHI_P_SS:
+	    vnum = 4;
+	    fsl = ((vtreg &gt;&gt; VF_SH_MR_VFSL) &amp; VF_MASK_MR_VFSL) &lt;&lt; 1;
+	    rxc = (vtreg &gt;&gt; VF_SH_MR_RXC) &amp; VF_MASK_MR_RXC;
+	    break;
+	  }
+	if (rxc)
+	  vtreg_s = (mtx &lt;&lt; VF_SH_MR_MTX) | (idx &lt;&lt; VF_SH_MR_FSL)
+		  | (fsl &lt;&lt; VF_SH_MR_IDX);
+	else
+	  vtreg_s = (mtx &lt;&lt; VF_SH_MR_MTX) | (idx &lt;&lt; VF_SH_MR_IDX)
+		  | (fsl &lt;&lt; VF_SH_MR_FSL);
+
+
+	for (i = 0; i &lt; vnum; i += 2) {
+	  f16v = ((vimm_expr[i + 1].X_add_number &amp; 0xffff) &lt;&lt; 16)
+	       | (vimm_expr[i].X_add_number &amp; 0xffff);
+	  sprintf(f16v_str, "0x%08x", f16v);
+	  my_getExpression (&amp;imm_expr, f16v_str);
+
+	  load_register (AT, &amp;imm_expr, 0);
+	  macro_build ((expressionS *) NULL,
+		       "mtv", "t,?d0z", AT, vtreg_s);
+
+	  if (rxc)
+	    vtreg_s += (1 &lt;&lt; VF_SH_MR_IDX);
+	  else
+	    vtreg_s += (1 &lt;&lt; VF_SH_MR_FSL);
+	}
+
+	break;
+      }
+
     case M_LI_D:
       /* Check if we have a constant in IMM_EXPR.  If the GPRs are 64 bits
          wide, IMM_EXPR is the entire value.  Otherwise IMM_EXPR is the high
@@ -6672,6 +7018,27 @@
       move_register (dreg, sreg);
       break;
 
+    case M_VCMOV_S:
+      s = "vcmovt.s";
+      fmt = "?d0d,?s0s,?e";
+      goto vcmov;
+    case M_VCMOV_P:
+      s = "vcmovt.p";
+      fmt = "?d1d,?s1s,?e";
+      goto vcmov;
+    case M_VCMOV_T:
+      s = "vcmovt.t";
+      fmt = "?d2d,?s2s,?e";
+      goto vcmov;
+    case M_VCMOV_Q:
+      s = "vcmovt.q";
+      fmt = "?d3d,?s3s,?e";
+    vcmov:
+      macro_build ((expressionS *) NULL, s, fmt,
+		   vdreg, vsreg,
+		   (ip-&gt;insn_opcode &gt;&gt; VF_SH_MCOND) &amp; VF_MASK_MCOND);
+      return;
+
 #ifdef LOSING_COMPILER
     default:
       /* Try and see if this is a new itbl instruction.
@@ -7348,6 +7715,39 @@
       move_register (treg, tempreg);
       break;
 
+    case M_ULV_S:
+      if (mips_opts.arch == CPU_ALLEGREX)
+	as_bad (_("opcode not supported on this processor"));
+      off = 3;
+      if (offset_expr.X_add_number &gt;= 0x8000 - off)
+	as_bad (_("operand overflow"));
+      if (! target_big_endian)
+	offset_expr.X_add_number += off;
+      macro_build (&amp;offset_expr, "lwl", "t,o(b)",
+		   AT, (int) BFD_RELOC_LO16, breg);
+      if (! target_big_endian)
+	offset_expr.X_add_number -= off;
+      else
+	offset_expr.X_add_number += off;
+      macro_build (&amp;offset_expr, "lwr", "t,o(b)",
+		   AT, (int) BFD_RELOC_LO16, breg);
+
+      macro_build ((expressionS *) NULL, "mtv", "t,?d0z",
+		   AT, vmreg);
+      break;
+
+    case M_ULV_Q:
+      off = 12;
+      if (offset_expr.X_add_number &gt;= 0x8000 - off)
+	as_bad (_("operand overflow"));
+      offset_expr.X_add_number += off;
+      macro_build (&amp;offset_expr, "lvl.q", "?n3x,?o(b)",
+		   vmreg, (int) BFD_RELOC_LO16, breg);
+      offset_expr.X_add_number -= off;
+      macro_build (&amp;offset_expr, "lvr.q", "?n3x,?o(b)",
+		   vmreg, (int) BFD_RELOC_LO16, breg);
+      return;
+
     case M_ULD_A:
       s = "ldl";
       s2 = "ldr";
@@ -7430,6 +7830,55 @@
       macro_build (&amp;offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
       break;
 
+    case M_USV_S:
+      off = 3;
+      if (offset_expr.X_add_number &gt;= 0x8000 - off)
+	as_bad (_("operand overflow"));
+      macro_build ((expressionS *) NULL, "mfv", "t,?d0z",
+		   AT, vmreg);
+      if (mips_opts.arch != CPU_ALLEGREX)
+	{
+	  if (! target_big_endian)
+	    offset_expr.X_add_number += off;
+	  macro_build (&amp;offset_expr, "swl", "t,o(b)",
+		       AT, (int) BFD_RELOC_LO16, breg);
+	  if (! target_big_endian)
+	    offset_expr.X_add_number -= off;
+	  else
+	    offset_expr.X_add_number += off;
+	  macro_build (&amp;offset_expr, "swr", "t,o(b)",
+		       AT, (int) BFD_RELOC_LO16, breg);
+	}
+      else
+	{
+	  if (target_big_endian)
+	    offset_expr.X_add_number += off;
+	  while (off-- &gt;= 0)
+	    {
+	      macro_build (&amp;offset_expr, "sb", "t,o(b)",
+			   AT, (int) BFD_RELOC_LO16, breg);
+	      macro_build ((expressionS *) NULL, "ror",
+			   "d,w,&lt;", AT, AT, 8);
+	      if (target_big_endian)
+		--offset_expr.X_add_number;
+	      else
+		++offset_expr.X_add_number;
+	    }
+	}
+      break;
+
+    case M_USV_Q:
+      off = 12;
+      if (offset_expr.X_add_number &gt;= 0x8000 - off)
+	as_bad (_("operand overflow"));
+      offset_expr.X_add_number += off;
+      macro_build (&amp;offset_expr, "svl.q", "?n3x,?o(b)",
+		   vmreg, (int) BFD_RELOC_LO16, breg);
+      offset_expr.X_add_number -= off;
+      macro_build (&amp;offset_expr, "svr.q", "?n3x,?o(b)",
+		   vmreg, (int) BFD_RELOC_LO16, breg);
+      return;
+
     case M_USD_A:
       s = "sdl";
       s2 = "sdr";
@@ -7817,6 +8266,103 @@
       case '%': USE_BITS (OP_MASK_VECALIGN,	OP_SH_VECALIGN); break;
       case '[': break;
       case ']': break;
+
+      /* VFPU fields */
+      case '?':
+	switch (c = *p++)
+	  {
+	  case '[': break;
+	  case ']': break;
+	  case 'y':
+	    {
+	      if ((*p != '0') &amp;&amp; (*p != '1') &amp;&amp; (*p != '2') &amp;&amp; (*p != '3'))
+		{
+		  as_bad (_("internal: bad mips opcode : %s %s"),
+			  opc-&gt;name, opc-&gt;args);
+		  return 0;
+		}
+	      p++;
+	    }
+	    break;
+
+	  case 'o': USE_BITS (VF_MASK_OFFSET,   VF_SH_OFFSET);  break;
+
+	  case 's':
+	  case 't':
+	  case 'd':
+	  case 'v':
+	  case 'x':
+	  case 'm':
+	  case 'n':
+	    {
+	      if ((*p != '0') &amp;&amp; (*p != '1') &amp;&amp; (*p != '2') &amp;&amp; (*p != '3')
+		  &amp;&amp; (*p != '5') &amp;&amp; (*p != '6') &amp;&amp; (*p != '7'))
+		{
+		  as_bad (_("internal: bad mips opcode (vreg type `?%c'): %s %s"),
+			  *p, opc-&gt;name, opc-&gt;args);
+		  return 0;
+		}
+	      p++;
+
+	      if ((*p != 's') &amp;&amp; (*p != 't') &amp;&amp; (*p != 'd')
+		  &amp;&amp; (*p != 'y') &amp;&amp; (*p != 'x') &amp;&amp; (*p != 'z')
+		  &amp;&amp; (*p != 'w') &amp;&amp; (*p != 'm'))
+		{
+		  as_bad (_("internal: bad mips opcode (vreg type `?%c'): %s %s"),
+			  *(p - 1), opc-&gt;name, opc-&gt;args);
+		}
+	      p++;
+
+	      switch (c)
+		{
+		case 's': USE_BITS (VF_MASK_VS,  VF_SH_VS);     break;
+		case 't': USE_BITS (VF_MASK_VT,  VF_SH_VT);     break;
+		case 'd':
+		case 'v':
+		case 'x': USE_BITS (VF_MASK_VD,  VF_SH_VD);     break;
+		case 'm': USE_BITS (VF_MASK_VML, VF_SH_VML);
+			  USE_BITS (VF_MASK_VMH, VF_SH_VMH);    break;
+		case 'n': USE_BITS (VF_MASK_VNL, VF_SH_VNL);
+			  USE_BITS (VF_MASK_VNH, VF_SH_VNH);    break;
+		}
+	    }
+	    break;
+
+	  case 'f': USE_BITS (VF_MASK_CC,       VF_SH_CC);
+		    p++;					break;
+
+	  case 'a': USE_BITS (VF_MASK_CONST,    VF_SH_CONST);   break;
+	  case 'b': USE_BITS (VF_MASK_SCALE,    VF_SH_SCALE);   break;
+	  case 'c': USE_BITS (VF_MASK_BCOND,    VF_SH_BCOND);   break;
+	  case 'e': USE_BITS (VF_MASK_MCOND,    VF_SH_MCOND);   break;
+
+	  case 'i': USE_BITS (VF_MASK_WRAP,     VF_SH_WRAP);    break;
+
+	  case 'q': USE_BITS (VF_MASK_VCD,      VF_SH_VCD);     break;
+	  case 'r': USE_BITS (VF_MASK_VCS,      VF_SH_VCS);     break;
+
+	  case 'u': USE_BITS (VF_MASK_HFLOAT,   VF_SH_HFLOAT);  break;
+
+	  case 'w': USE_BITS (VF_MASK_ROT,      VF_SH_ROT);     break;
+	  case 'z': USE_BITS (VF_MASK_RWB,      VF_SH_RWB);     break;
+
+	  case '0': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+	  case '1': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+	  case '2': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+	  case '3': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+	  case '4': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+	  case '5': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+	  case '6': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+	  case '7': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+
+	  default:
+	    as_bad (_("internal: bad mips opcode (unknown extension operand type `?%c'): %s %s"),
+		    c, opc-&gt;name, opc-&gt;args);
+	    return 0;
+
+	  }
+	break;
+
       default:
 	as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
 		c, opc-&gt;name, opc-&gt;args);
@@ -7845,12 +8391,15 @@
   char c = 0;
   struct mips_opcode *insn;
   char *argsStart;
-  unsigned int regno;
+  unsigned int regno = 0;
   unsigned int lastregno = 0;
   unsigned int lastpos = 0;
   unsigned int limlo, limhi;
   char *s_reset;
   char save_c = 0;
+  unsigned int vdregno = 0xffff;
+  char vdregt = 0;
+  char vdregl = 0;
 
   insn_error = NULL;
 
@@ -8238,26 +8787,1171 @@
 	      s = expr_end;
 	      continue;
 
-	    case 'b':		/* base register */
-	    case 'd':		/* destination register */
-	    case 's':		/* source register */
-	    case 't':		/* target register */
-	    case 'r':		/* both target and source */
-	    case 'v':		/* both dest and source */
-	    case 'w':		/* both dest and target */
-	    case 'E':		/* coprocessor target register */
-	    case 'G':		/* coprocessor destination register */
-	    case 'K':		/* 'rdhwr' destination register */
-	    case 'x':		/* ignore register name */
-	    case 'z':		/* must be zero register */
-	    case 'U':           /* destination register (clo/clz).  */
-	      s_reset = s;
-	      if (s[0] == '$')
+	    /* VFPU fields */
+	    case '?':
+	    switch (*++args)
 		{
+	      case '[':
+	      case ']':
+		if (*s++ == *args)
+		  continue;
+		break;
 
-		  if (ISDIGIT (s[1]))
-		    {
-		      ++s;
+	      case 'y':		/* immediate separator */
+		++args;
+		vimm_expr[*args - '0'] = imm_expr;
+		voffset_expr[*args - '0'] = offset_expr;
+
+		imm_expr.X_op = O_absent;
+		offset_expr.X_op = O_absent;
+		imm_reloc[0] = BFD_RELOC_UNUSED;
+		imm_reloc[1] = BFD_RELOC_UNUSED;
+		imm_reloc[2] = BFD_RELOC_UNUSED;
+		offset_reloc[0] = BFD_RELOC_UNUSED;
+		offset_reloc[1] = BFD_RELOC_UNUSED;
+		offset_reloc[2] = BFD_RELOC_UNUSED;
+
+		continue;
+
+	      case 'o':		/* 16 bit offset */
+		/* Check whether there is only a single bracketed expression
+		   left.  If so, it must be the base register and the
+		   constant must be zero.  */
+		if (*s == '(' &amp;&amp; strchr (s + 1, '(') == 0)
+		  {
+		    offset_expr.X_op = O_constant;
+		    offset_expr.X_add_number = 0;
+		    continue;
+		  }
+
+		/* If this value won't fit into a 16 bit offset, then go
+		   find a macro that will generate the 32 bit offset
+		   code pattern.  */
+		if (my_getSmallExpression (&amp;offset_expr, offset_reloc, s) == 0
+		    &amp;&amp; (offset_expr.X_op != O_constant
+			|| offset_expr.X_add_number &gt;= 0x8000
+			|| offset_expr.X_add_number &lt; -0x8000))
+		  break;
+
+		s = expr_end;
+		continue;
+
+	      case 's':		/* VFPU source register */
+	      case 't':		/* VFPU target register */
+	      case 'd':		/* VFPU destination register */
+	      case 'v':		/* VFPU destination register */
+	      case 'x':		/* VFPU destination register */
+	      case 'm':		/* VFPU target regsiter (load/store) */
+	      case 'n':		/* VFPU target regsiter (load/store) */
+		{
+		  int dtype_err = 0;
+		  int dnum_err = 0;
+		  int dlen = 0;
+		  char dtype = s[0];
+		  char regtype = *(args + 1);
+
+		  int mtx = 0;
+		  int idx = 0;
+		  int rxc = 0;
+		  int fsl = 0;
+		  int vidx = 0;
+		  int vfsl = 0;
+
+		  if (ISDIGIT (s[1]))
+		    {
+		      int num = 0;
+		      s++;
+		      do
+			{
+			  num *= 10;
+			  num += *s - '0';
+			  dlen++;
+			  s++;
+			}
+		      while (ISDIGIT (*s));
+
+		      if ((s[0] == '.')
+			  &amp;&amp; (s[1] == 's' || s[1] == 'p'
+			      || s[1] == 't' || s[1] == 'q'))
+			s += 2;
+
+		      if (ISUPPER(dtype))
+			dtype -= 'A' - 'a';
+
+		      if (dtype == '$')
+			{
+			  regno = num;
+			  if (regno &gt; VF_MAX_MR)
+			    as_bad (_("Invalid VFPU register number (%d)"),
+				    regno);
+
+			  idx = (num &gt;&gt; VF_SH_MR_IDX) &amp; VF_MASK_MR_IDX;
+			  vfsl = (num &gt;&gt; VF_SH_MR_VFSL) &amp; VF_MASK_MR_VFSL;
+			  switch (regtype)
+			    {
+			    case '0':	/* single word */
+			      break;
+			    case '1':	/* pare word */
+			      dnum_err = (vfsl &amp; 0x1);
+			      break;
+			    case '2':	/* triple word */
+			      dnum_err = (vfsl &gt; 1);
+			      break;
+			    case '3':	/* quad word */
+			      dnum_err = (vfsl &gt; 0);
+			      break;
+			    case '5':	/* 2x2 word */
+			      dnum_err = (vfsl &amp; 0x1) || (idx &amp; 0x1);
+			      break;
+			    case '6':	/* 3x3 word */
+			      dnum_err = (vfsl &gt; 1) || (idx &gt; 1);
+			      break;
+			    case '7':	/* 4x4 word */
+			      dnum_err = (vfsl &gt; 0) || (idx &gt; 0);
+			      break;
+			    }
+
+			  if (dnum_err)
+			    as_bad (_("Improper VFPU register number (%d)"),
+				     regno);
+
+			}
+		      else if ((dlen == 3)
+			       &amp;&amp; ((dtype == 's')
+				   || (dtype == 'c') || (dtype == 'r')
+				   || (dtype == 'm') || (dtype == 'e')))
+			{
+			  mtx = num / 100;
+			  if ((dtype == 'r') || (dtype == 'e'))
+			    {
+			      vfsl = (num / 10) % 10;
+			      vidx = num % 10;
+			      rxc = 1;
+			    }
+			  else
+			    {
+			      vidx = (num / 10) % 10;
+			      vfsl = num % 10;
+			      rxc = 0;
+			    }
+
+			  switch (regtype)
+			    {
+			    case '0':	/* single word */
+			      idx = vidx;
+			      fsl = vfsl;
+			      dtype_err = (dtype != 's');
+			      break;
+			    case '1':	/* pare word */
+			      idx = vidx;
+			      fsl = (vfsl &amp; 0x2) | rxc;
+			      dnum_err = (vfsl &amp; 0x1);
+			      dtype_err = (dtype != 'c') &amp;&amp; (dtype != 'r');
+			      break;
+			    case '2':	/* triple word */
+			      idx = vidx;
+			      fsl = ((vfsl &amp; 0x1) &lt;&lt; 1) | rxc;
+			      dnum_err = (vfsl &gt; 1);
+			      dtype_err = (dtype != 'c') &amp;&amp; (dtype != 'r');
+			      break;
+			    case '3':	/* quad word */
+			      idx = vidx;
+			      fsl = rxc;
+			      dnum_err = (vfsl &gt; 0);
+			      dtype_err = (dtype != 'c') &amp;&amp; (dtype != 'r');
+			      break;
+			    case '5':	/* 2x2 word */
+			      idx = vidx &amp; 0x2;
+			      fsl = (vfsl &amp; 0x2) | rxc;
+			      dnum_err = (vfsl &amp; 0x1) || (vidx &amp; 0x1);
+			      dtype_err = (dtype != 'm') &amp;&amp; (dtype != 'e');
+			      break;
+			    case '6':	/* 3x3 word */
+			      idx = vidx &amp; 0x1;
+			      fsl = ((vfsl &amp; 0x1) &lt;&lt; 1) | rxc;
+			      dnum_err = (vfsl &gt; 1) || (vidx &gt; 1);
+			      dtype_err = (dtype != 'm') &amp;&amp; (dtype != 'e');
+			      break;
+			    case '7':	/* 4x4 word */
+			      idx = 0;
+			      fsl = rxc;
+			      dnum_err = (vfsl &gt; 0) || (vidx &gt; 0);
+			      dtype_err = (dtype != 'm') &amp;&amp; (dtype != 'e');
+			      break;
+			    }
+
+			  if (dtype_err)
+			    as_bad (_("Improper VFPU register prefix '%c'"),
+				     dtype);
+			  if (dnum_err)
+			    as_bad (_("Improper VFPU register number (%03d)"),
+				     num);
+
+			  if (mtx &gt; VF_MAX_MR_MTX)
+			    as_bad (_("VFPU matrix range over %d"), mtx);
+			  if (vidx &gt; VF_MAX_MR_IDX)
+			    as_bad (_("VFPU index range over %d"), idx);
+			  if (vfsl &gt; VF_MAX_MR_FSL)
+			    as_bad (_("VFPU field select range over %d"), fsl);
+	      
+			  regno = ((fsl &amp; VF_MASK_MR_FSL) &lt;&lt; VF_SH_MR_FSL)
+				| ((mtx &amp; VF_MASK_MR_MTX) &lt;&lt; VF_SH_MR_MTX)
+				| ((idx &amp; VF_MASK_MR_IDX) &lt;&lt; VF_SH_MR_IDX);
+			}
+		      else
+			{
+			    as_bad (_("Improper VFPU register prefix '%c'"),
+				     dtype);
+			}
+		    }
+		  else
+		    {
+		      as_bad (_("bad operand %s"), s);
+		    }
+
+		  if ((*args == 'v') || (*args == 'x'))
+		    {
+		      vdregno = regno;
+		      vdregt = regtype;
+		      vdregl = (*args == 'v');
+		    }
+		  else if (vdregno &lt;= VF_MAX_MR)
+		    {
+		      static unsigned short used_vreg[8][16] = {
+			{ 0x0001, 0x0010, 0x0100, 0x1000,
+			  0x0002, 0x0020, 0x0200, 0x2000,
+			  0x0004, 0x0040, 0x0400, 0x4000,
+			  0x0008, 0x0080, 0x0800, 0x8000 },
+			{ 0x0003, 0x0030, 0x0300, 0x3000,
+			  0x0011, 0x0022, 0x0044, 0x0088,
+			  0x000c, 0x00c0, 0x0c00, 0xc000,
+			  0x1100, 0x2200, 0x4400, 0x8800 },
+			{ 0x0007, 0x0070, 0x0700, 0x7000,
+			  0x0111, 0x0222, 0x0444, 0x0888,
+			  0x000e, 0x00e0, 0x0e00, 0xe000,
+			  0x1110, 0x2220, 0x4440, 0x8880 },
+			{ 0x000f, 0x00f0, 0x0f00, 0xf000,
+			  0x1111, 0x2222, 0x4444, 0x8888,
+			  0x000f, 0x00f0, 0x0f00, 0xf000,
+			  0x1111, 0x2222, 0x4444, 0x8888 },
+			{ 0x0000, 0x0000, 0x0000, 0x0000,
+			  0x0000, 0x0000, 0x0000, 0x0000,
+			  0x0000, 0x0000, 0x0000, 0x0000,
+			  0x0000, 0x0000, 0x0000, 0x0000 },
+			{ 0x0033, 0x0033, 0x3300, 0x3300,
+			  0x0033, 0x0033, 0x00cc, 0x00cc,
+			  0x00cc, 0x00cc, 0xcc00, 0xcc00,
+			  0x3300, 0x3300, 0xcc00, 0xcc00 },
+			{ 0x0777, 0x7770, 0x0777, 0x7770,
+			  0x0777, 0x0eee, 0x0777, 0x0eee,
+			  0x0eee, 0xeee0, 0x0eee, 0xeee0,
+			  0x7770, 0xeee0, 0x7770, 0xeee0 },
+			{ 0xffff, 0xffff, 0xffff, 0xffff,
+			  0xffff, 0xffff, 0xffff, 0xffff,
+     			  0xffff, 0xffff, 0xffff, 0xffff,
+			  0xffff, 0xffff, 0xffff, 0xffff },
+		      };
+		      int dmtx, smtx;
+		      int dfsl, sfsl;
+		      int didx, sidx;
+		      int drxc, srxc;
+
+		      dmtx = (vdregno &gt;&gt; VF_SH_MR_MTX) &amp; VF_MASK_MR_MTX;
+		      smtx = (regno   &gt;&gt; VF_SH_MR_MTX) &amp; VF_MASK_MR_MTX;
+
+		      if (dmtx == smtx)
+			{
+			  unsigned short dused, sused;
+			  int dtype, stype;
+
+			  dfsl = (vdregno &gt;&gt; VF_SH_MR_FSL) &amp; VF_MASK_MR_FSL;
+			  didx = (vdregno &gt;&gt; VF_SH_MR_IDX) &amp; VF_MASK_MR_IDX;
+			  drxc = (vdregno &gt;&gt; VF_SH_MR_RXC) &amp; VF_MASK_MR_RXC;
+			  sfsl = (regno   &gt;&gt; VF_SH_MR_FSL) &amp; VF_MASK_MR_FSL;
+			  sidx = (regno   &gt;&gt; VF_SH_MR_IDX) &amp; VF_MASK_MR_IDX;
+			  srxc = (regno   &gt;&gt; VF_SH_MR_RXC) &amp; VF_MASK_MR_RXC;
+
+			  dtype = vdregt - '0';
+			  stype = regtype - '0';
+			  dused = used_vreg[dtype][(dfsl &lt;&lt; 2) + didx];
+			  sused = used_vreg[stype][(sfsl &lt;&lt; 2) + sidx];
+
+			  if ((dused &amp; sused)
+			      &amp;&amp; (vdregl || (dused ^ sused) || (drxc != srxc)))
+			    {
+			      int dvfsl;
+			      dvfsl = (vdregno &gt;&gt; VF_SH_MR_VFSL) &amp; VF_MASK_MR_VFSL;
+			      switch (vdregt)
+				{
+				case '1':
+				  dvfsl &lt;&lt;= 1;
+				case '2':
+				case '3':
+				  if (drxc)
+				    as_bad (_("VFPU register conflict(R%d%d%d)"),
+					     dmtx, dvfsl, didx);
+				  else
+				    as_bad (_("VFPU register conflict(C%d%d%d)"),
+					     dmtx, didx, dvfsl);
+				  break;
+				case '5':
+				  dvfsl &lt;&lt;= 1;
+				case '6':
+				case '7':
+				  if (drxc)
+				    as_bad (_("VFPU register conflict(E%d%d%d)"),
+					     dmtx, dvfsl, didx);
+				  else
+				    as_bad (_("VFPU register conflict(M%d%d%d)"),
+					     dmtx, didx, dvfsl);
+				  break;
+				}
+			    }
+			}
+		    }
+
+		  switch (*args++)
+		    {
+		    case 's':
+		      if (
+			  (ip-&gt;insn_opcode
+			      &amp; VFPU_MASK_RPT_MMUL) == VFPU_INST_RPT_MMUL)
+			{
+			  if (regno &amp; (VF_MASK_MR_RXC &lt;&lt; VF_SH_MR_RXC))
+			    regno &amp;= ~(VF_MASK_MR_RXC &lt;&lt; VF_SH_MR_RXC);
+			  else
+			    regno |= (VF_MASK_MR_RXC &lt;&lt; VF_SH_MR_RXC);
+			}
+		      ip-&gt;insn_opcode |= (regno &amp; VF_MASK_VS) &lt;&lt; VF_SH_VS;
+		      break;
+		    case 't':
+		      ip-&gt;insn_opcode |= (regno &amp; VF_MASK_VT) &lt;&lt; VF_SH_VT;
+		      break;
+		    case 'd':
+		    case 'v':
+		    case 'x':
+		      ip-&gt;insn_opcode |= (regno &amp; VF_MASK_VD) &lt;&lt; VF_SH_VD;
+		      break;
+		    case 'm':
+		      {
+			int vmregL = (regno &gt;&gt; 0) &amp; VF_MASK_VML;
+			int vmregH = (regno &gt;&gt; 5) &amp; VF_MASK_VMH;
+			ip-&gt;insn_opcode |= (vmregL &lt;&lt; VF_SH_VML)
+					| (vmregH &lt;&lt; VF_SH_VMH);
+		      }
+		      break;
+		    case 'n':
+		      {
+			int vmregL = (regno &gt;&gt; 0) &amp; VF_MASK_VNL;
+			int vmregH = (regno &gt;&gt; 5) &amp; VF_MASK_VNH;
+			ip-&gt;insn_opcode |= (vmregL &lt;&lt; VF_SH_VNL)
+					| (vmregH &lt;&lt; VF_SH_VNH);
+		      }
+		      break;
+		    }
+		  args++;
+
+		  /* now check for vfpu prefixes if necessary */
+		  if (*s == '[')
+		    {
+		      char *prefix_out = NULL;
+		      bfd_boolean *prefix_bool = NULL;
+		      char *prefix_type = NULL;
+		      int num_args = 0;
+		      char *ob = ++s;
+		      bfd_boolean has_w = FALSE;
+		      bfd_boolean has_z = FALSE;
+		      bfd_boolean has_y = FALSE;
+		      bfd_boolean has_operator = FALSE;
+		      bfd_boolean has_saturater = FALSE;
+
+		      switch (*args)
+			{
+			case 'w':	/* only swizzle */
+			case 's':	/* source prefix */
+			  prefix_bool = &amp;vfpu_sprefix;
+			  prefix_out = vfpu_sprefix_str;
+			  prefix_type = "source";
+			  break;
+			case 't':	/* target prefix */
+			  prefix_bool = &amp;vfpu_tprefix;
+			  prefix_out = vfpu_tprefix_str;
+			  prefix_type = "target";
+			  break;
+			case 'm':	/* only write mask */
+			case 'd':	/* destination prefix */
+			  prefix_bool = &amp;vfpu_dprefix;
+			  prefix_out = vfpu_dprefix_str;
+			  prefix_type = "destination";
+			  break;
+			case 'y':	/* inhibit */
+			  prefix_bool = NULL;
+			  prefix_type = "source";
+			  break;
+			case 'x':	/* inhibit */
+			  prefix_bool = NULL;
+			  prefix_type = "target";
+			  break;
+			case 'z':	/* inhibit */
+			  prefix_bool = NULL;
+			  prefix_type = "destination";
+			  break;
+			}
+
+		      for ( ; *s != '\0' &amp;&amp; *s != ']'; s++)
+			{
+			  switch (*s)
+			    {
+			    case ',':
+			      /* count no. of params for syntax check */
+			      num_args++;
+			      break;
+			    case ' ':
+			    case '\t':
+			      break;
+			    case 'm':
+			    case 'M':
+			    case 'x':
+			    case 'X':
+			      break;
+			    case 'y':
+			    case 'Y':
+			      has_y = TRUE;
+			      break;
+			    case 'z':
+			    case 'Z':
+			      has_z = TRUE;
+			      break;
+			    case 'w':
+			    case 'W':
+			      has_w = TRUE;
+			      break;
+			    default:
+			      if (*args == 'w')
+				has_operator = TRUE;
+			      if (*args == 'm')
+				has_saturater = TRUE;
+			    }
+			}
+
+		      if (*s == ']')
+			{
+			  if (prefix_bool)
+			    {
+			      *prefix_bool = TRUE;
+			      strncpy (prefix_out, ob, s - ob);
+			      prefix_out[s - ob] = '\0';
+			      s++;
+			    }
+			  else
+			    {
+			      as_bad (_("%s cannot use %s prefix"),
+				      insn-&gt;name, prefix_type);
+			      s++;
+			      continue;
+			    }
+			}
+		      else
+			{
+			  as_bad (_("parse error (%s)"), ob - 1);
+			  return;
+			}
+
+		      if (num_args != regtype - '0')
+			{
+			  as_bad (_("%s prefix specification requires %d parameters - [%s]"),
+				  prefix_type, regtype - '0' + 1,
+				  prefix_out);
+			}
+		      else
+			{
+			  int i = 8 - ((3 - num_args) * 2);
+			  char dummy_d[] = " m,m,m,m";
+			  char dummy_st[] = " x,y,z,w";
+
+			  if (*args == 'd' || *args == 'm')
+			    {
+			      strcat (prefix_out, dummy_d + i);
+			      if (has_saturater)
+				{
+				  as_bad (_("%s is restricted to mask destination prefixes only"),
+					  insn-&gt;name);
+				}
+			    }
+			  else
+			    {
+			      strcat (prefix_out, dummy_st + i);
+			      if (has_operator)
+				{
+				  as_bad (_("%s is restricted to swizzle %s prefixes only"),
+					  insn-&gt;name, prefix_type);
+				}
+			      /* semantic check, w can't be specified for
+				 s, p, or t instructions same goes for
+				 z for p and s, and y for scalars */
+			      if ((has_y &amp;&amp; num_args == 0)
+				  || (has_z &amp;&amp; num_args &lt; 2)
+				  || (has_w &amp;&amp; num_args &lt; 3))
+				{
+				  as_bad (_("%s swizzle operand is out of range in [%s]"),
+					  prefix_type, prefix_out);
+				}
+			    }
+			}
+		    }
+
+		  continue;
+		}
+		break;
+
+	      case 'q':		/* VFPU destination control register */
+	      case 'r':		/* VFPU source control register */
+		{
+		  if ((s[0] == '$') &amp;&amp; ISDIGIT (s[1]))
+		    {
+		      s++;
+		      regno = 0;
+		      do
+			{
+			  regno *= 10;
+			  regno += *s - '0';
+			  ++s;
+			}
+		      while (ISDIGIT (*s));
+
+		      if ((regno &lt; VF_MIN_CR) || (regno &gt; VF_MAX_CR))
+			as_bad (_("Invalid VFPU control register number (%d)"),
+				 regno);
+
+		      else if (!((regno &gt;= VF_MIN_VCR) &amp;&amp; (regno &lt;= VF_MAX_VCR)))
+			as_bad (_("Improper VFPU control register number (%d)"),
+				 regno);
+
+		      switch (*args)
+			{
+			case 'q':
+			  ip-&gt;insn_opcode |= (regno &amp; VF_MASK_VCD) &lt;&lt; VF_SH_VCD;
+			  break;
+			case 'r':
+			  ip-&gt;insn_opcode |= (regno &amp; VF_MASK_VCS) &lt;&lt; VF_SH_VCS;
+			  break;
+			}
+		    }
+		  else
+		    {
+		      as_bad (_("Invalid VFPU control register name (%s)"), s);
+		    }
+
+		  continue;
+		}
+		break;
+
+	      case 'f':		/* condition code */
+		{
+		  int cond = 0;
+		  if (ISDIGIT (s[0]))
+		    {
+		      my_getExpression (&amp;imm_expr, s);
+		      check_absolute_expr (ip, &amp;imm_expr);
+		      cond = imm_expr.X_add_number;
+		      if ((cond &lt; VF_MIN_CC) || (cond &gt; VF_MAX_CC))
+			as_bad (_("Invalid VFPU condition code (%d)"), cond);
+		      imm_expr.X_op = O_absent;
+		      s = expr_end;
+		    }
+		  else
+		    {
+		      static const char * const vfpu_cond_names[] = {
+			"FL", "EQ", "LT", "LE",
+			"TR", "NE", "GE", "GT",
+			"EZ", "EN", "EI", "ES",
+			"NZ", "NN", "NI", "NS" };
+		      for (cond = VF_MIN_CC; cond &lt;= VF_MAX_CC; cond++)
+			{
+			  if (strncasecmp(vfpu_cond_names[cond], s, 2) == 0)
+			    break;
+			}
+		      if ((cond &lt; VF_MIN_CC) || (cond &gt; VF_MAX_CC))
+			as_bad (_("Invalid VFPU condition code (%s)"), s);
+
+		      s += 2;
+		    }
+
+		  args++;
+		  if ((cond == 0) || (cond == 4))
+		    {
+		    }
+		  else if (cond &amp; 0x8)
+		    {
+		      if (*args - '0' &lt; 1)
+			as_bad (_("Invalid VFPU condition oparetion"));
+		    }
+		  else
+		    {
+		      if (*args - '0' &lt; 2)
+			as_bad (_("Invalid VFPU condition oparetion"));
+		    }
+
+		  ip-&gt;insn_opcode |= (cond &amp; VF_MASK_CC) &lt;&lt; VF_SH_CC;
+		  continue;
+		}
+		break;
+
+	      case 'a':		/* constant code */
+		{
+		  int cst = 0;
+		  if (ISDIGIT (s[0]))
+		    {
+		      my_getExpression (&amp;imm_expr, s);
+		      check_absolute_expr (ip, &amp;imm_expr);
+		      cst = imm_expr.X_add_number;
+		      if ((cst &lt; VF_MIN_CONST) || (cst &gt; VF_MAX_CONST))
+			{
+			  as_bad (_("Improper constant code (%d)"), cst);
+			  cst &amp;= VF_MASK_CONST;
+			}
+		      imm_expr.X_op = O_absent;
+		      s = expr_end;
+		    }
+		  else
+		    {
+		      static const char * const vfpu_const_names[] = {
+			"", "VFPU_HUGE", "VFPU_SQRT2", "VFPU_SQRT1_2",
+			"VFPU_2_SQRTPI", "VFPU_2_PI", "VFPU_1_PI", "VFPU_PI_4",
+			"VFPU_PI_2", "VFPU_PI", "VFPU_E", "VFPU_LOG2E",
+			"VFPU_LOG10E", "VFPU_LN2", "VFPU_LN10", "VFPU_2PI",
+			"VFPU_PI_6", "VFPU_LOG10TWO", "VFPU_LOG2TEN",
+			"VFPU_SQRT3_2"};
+		      for (cst = VF_MIN_CONST; cst &lt;= VF_MAX_CONST; cst++)
+			{
+			  if (strcasecmp(vfpu_const_names[cst], s) == 0)
+			    break;
+			}
+		      if ((cst &lt; VF_MIN_CONST) || (cst &gt; VF_MAX_CONST))
+			as_bad (_("Invalid constant code (%s)"), s);
+		      else
+			s += strlen(vfpu_const_names[cst]);
+		    }
+
+		  ip-&gt;insn_opcode |= cst &lt;&lt; VF_SH_CONST;
+		}
+		continue;
+
+	      case 'b':		/* scale exponent */
+		my_getExpression (&amp;imm_expr, s);
+		check_absolute_expr (ip, &amp;imm_expr);
+		if ((unsigned long) imm_expr.X_add_number &gt; VF_MAX_SCALE)
+		  {
+		    as_bad (_("Improper scale (%lu)"),
+			     (unsigned long) imm_expr.X_add_number);
+		    imm_expr.X_add_number &amp;= VF_MASK_SCALE;
+		  }
+		ip-&gt;insn_opcode |= imm_expr.X_add_number &lt;&lt; VF_SH_SCALE;
+		imm_expr.X_op = O_absent;
+		s = expr_end;
+		continue;
+
+	      case 'c':		/* branch condition code bit */
+		my_getExpression (&amp;imm_expr, s);
+		check_absolute_expr (ip, &amp;imm_expr);
+		if ((unsigned long) imm_expr.X_add_number &gt; VF_MAX_BCOND)
+		  {
+		    as_bad (_("Improper condition bit (%lu)"),
+			     (unsigned long) imm_expr.X_add_number);
+		    imm_expr.X_add_number &amp;= VF_MASK_BCOND;
+		  }
+		ip-&gt;insn_opcode |= imm_expr.X_add_number &lt;&lt; VF_SH_BCOND;
+		imm_expr.X_op = O_absent;
+		s = expr_end;
+		continue;
+
+	      case 'e':		/* move condition code bit */
+		my_getExpression (&amp;imm_expr, s);
+		check_absolute_expr (ip, &amp;imm_expr);
+		if ((unsigned long) imm_expr.X_add_number &gt; VF_MAX_MCOND)
+		  {
+		    as_bad (_("Improper condition bit (%lu)"),
+			     (unsigned long) imm_expr.X_add_number);
+		    imm_expr.X_add_number &amp;= VF_MASK_MCOND;
+		  }
+		ip-&gt;insn_opcode |= imm_expr.X_add_number &lt;&lt; VF_SH_MCOND;
+		imm_expr.X_op = O_absent;
+		s = expr_end;
+		continue;
+
+	      case 'i':		/* wrap exponent */
+		my_getExpression (&amp;imm_expr, s);
+		check_absolute_expr (ip, &amp;imm_expr);
+		if ((unsigned long) imm_expr.X_add_number &gt; VF_MAX_WRAP)
+		  {
+		    as_bad (_("Improper wrap (%lu)"),
+			     (unsigned long) imm_expr.X_add_number);
+		    imm_expr.X_add_number &amp;= VF_MASK_WRAP;
+		  }
+		ip-&gt;insn_opcode |= imm_expr.X_add_number &lt;&lt; VF_SH_WRAP;
+		imm_expr.X_op = O_absent;
+		s = expr_end;
+		continue;
+
+	      case 'w':		/* rotation code */
+		if (s[0] == '[')
+		  {
+		    char *rot_str = s;
+		    int rot_idx = 0;
+		    int rot_neg = 0;
+		    int rot_sin = 3;
+		    int rot_cos = 3;
+		    int rot_err = 0;
+		    int rot_n;
+		    int rot_neg_n = 0;
+		    int rot_sin_n = 0;
+		    int rot_cos_n = 0;
+		    int rot_code;
+
+		    if ((ip-&gt;insn_opcode &amp; VFPU_MASK_DTYPE) == VFPU_PAIR)
+		      rot_n = 2;
+		    else if ((ip-&gt;insn_opcode &amp; VFPU_MASK_DTYPE) == VFPU_TRIPLE)
+		      rot_n = 3;
+		    else if ((ip-&gt;insn_opcode &amp; VFPU_MASK_DTYPE) == VFPU_QUAD)
+		      rot_n = 4;
+		    else
+		      rot_n = 0;
+
+		    s++;
+		    while ((s[0] != ']') &amp;&amp; (s[0] != '\0'))
+		      {
+			if (s[0] == '-')
+			  {
+			    if ((s[1] != 's') &amp;&amp; (s[1] != 'S'))
+			      {
+				rot_err = 1;
+				break;
+			      }
+			    rot_neg = 1;
+			    rot_neg_n++;
+			    s++;
+			  }
+
+			if (s[0] == ',')
+			  rot_idx++;
+			else if ((s[0] == 'c') || (s[0] == 'C'))
+			  {
+			    rot_cos = rot_idx;
+			    rot_cos_n++;
+			  }
+			else if ((s[0] == 's') || (s[0] == 'S'))
+			  {
+			    rot_sin = rot_idx;
+			    rot_sin_n++;
+			  }
+			else if (ISSPACE(s[0]) || (s[0] == '0'))
+			  ;
+			else
+			  {
+			    rot_err = 1;
+			    break;
+			  }
+
+			s++;
+		      }
+
+		    if (s[0] == ']')
+		      rot_idx++;
+		    else
+		      rot_err = 1;
+		    s++;
+
+		    if ((rot_sin_n == 0) &amp;&amp; (rot_cos_n == 0))
+		      {
+			if (rot_n == 2)
+			  rot_sin = 2;
+			else if ((rot_n == 4) || (rot_n == 3))
+			  rot_err = 1;
+		      }
+
+		    if (rot_cos_n &gt; 1)
+		      rot_err = 1;
+
+		    if (rot_sin_n &gt; 1)
+		      {
+			if (((rot_sin_n + rot_cos_n) != rot_n)
+			    || ((rot_n == 4) &amp;&amp; (rot_cos_n == 0)))
+			  rot_err = 1;
+		      }
+
+		    if (rot_neg &amp;&amp; (rot_neg_n != rot_sin_n))
+		      rot_err = 1;
+
+		    if (rot_sin_n &gt; 1)
+		      rot_sin = rot_cos;
+
+		    if (rot_err || (rot_n != rot_idx))
+		      as_bad (_("Invalid rotation code (%s)"), rot_str);
+
+		    rot_code = ((rot_neg &amp; VF_MASK_ROT_NEG) &lt;&lt; VF_SH_ROT_NEG)
+			     | ((rot_cos &amp; VF_MASK_ROT_COS) &lt;&lt; VF_SH_ROT_COS)
+			     | ((rot_sin &amp; VF_MASK_ROT_SIN) &lt;&lt; VF_SH_ROT_SIN);
+		    ip-&gt;insn_opcode |= rot_code &lt;&lt; VF_SH_ROT;
+		  }
+		else
+		  {
+		    my_getExpression (&amp;imm_expr, s);
+		    check_absolute_expr (ip, &amp;imm_expr);
+		    if ((unsigned long) imm_expr.X_add_number &gt; VF_MAX_ROT)
+		      {
+			as_bad (_("Improper rotation code (%lu)"),
+				 (unsigned long) imm_expr.X_add_number);
+			imm_expr.X_add_number &amp;= VF_MASK_ROT;
+		      }
+		    ip-&gt;insn_opcode |= imm_expr.X_add_number &lt;&lt; VF_SH_ROT;
+		    imm_expr.X_op = O_absent;
+		    s = expr_end;
+		  }
+		continue;
+
+	      case 'u':		/* half float */
+		if ((s[0] == '0') &amp;&amp; ((s[1] == 'x') || (s[1] == 'X')))
+		  {
+		    my_getExpression (&amp;imm_expr, s);
+		    check_absolute_expr (ip, &amp;imm_expr);
+		    if ((unsigned long) imm_expr.X_add_number &gt; VF_MAX_HFLOAT)
+		      {
+			as_bad (_("Improper half floating point constant: (%lu)"),
+				(unsigned long) imm_expr.X_add_number);
+			imm_expr.X_add_number &amp;= VF_MASK_HFLOAT;
+		      }
+		    ip-&gt;insn_opcode |= imm_expr.X_add_number &lt;&lt; VF_SH_HFLOAT;
+		    imm_expr.X_op = O_absent;
+		    s = expr_end;
+		    continue;
+		  }
+		else
+		  {
+		    char *save_in;
+		    char *err;
+		    int len;
+		    unsigned int length;
+		    unsigned char temp[8];
+		    unsigned int f32, f16;
+		    int exponent32, exponent16;
+		    int fraction32, fraction16;
+		    int sign;
+		    char f16_str[8];
+
+		    save_in = input_line_pointer;
+		    input_line_pointer = s;
+		    err = md_atof ('f', (char *) temp, &amp;len);
+		    length = len;
+		    s = input_line_pointer;
+		    input_line_pointer = save_in;
+		    if (err != NULL &amp;&amp; *err != '\0')
+		      {
+			as_bad (_("Bad half floating point constant: %s"), err);
+			memset (temp, '\0', sizeof temp);
+			length = 4;
+		      }
+
+		    if (! target_big_endian)
+		      f32 = bfd_getl32 (temp);
+		    else
+		      f32 = bfd_getb32 (temp);
+
+		    sign = (f32 &gt;&gt; VF_SH_F32_SIGN) &amp; VF_MASK_F32_SIGN;
+		    exponent32 = (f32 &gt;&gt; VF_SH_F32_EXP) &amp; VF_MASK_F32_EXP;
+		    fraction32 = (f32 &gt;&gt; VF_SH_F32_FRA) &amp; VF_MASK_F32_FRA;
+		    exponent16 = exponent32
+			       - VF_BIAS_F32_EXP + VF_BIAS_F16_EXP;
+
+		    if (exponent16 &lt; VF_MIN_F16_EXP)
+		      {
+			if ((exponent32 == VF_MIN_F32_EXP)
+			    &amp;&amp; (fraction32 == 0))
+			  { // zero
+			    exponent16 = VF_MIN_F16_EXP;
+			    fraction16 = 0;
+			  }
+			else
+			  { // underflow
+				  float* p;
+				  p = (float*) &amp;f32;
+			    as_warn (_("Half floating point underflow: %g"),
+				     *p);
+			    exponent16 = VF_MIN_F16_EXP;
+			    fraction16 = 0;
+			  }
+		      }
+		    else if (exponent16 &gt; VF_MAX_F16_EXP)
+		      {
+			if (exponent32 != VF_MAX_F32_EXP)
+			  { // overflow
+			    as_warn (_("Half floating point overflow: %g"),
+				     *(float *)&amp;f32);
+			    exponent16 = VF_MAX_F16_EXP;
+			    fraction16 = 0;
+			  }
+			else
+			  {
+			    if (fraction32 == 0)
+			      { // infinity
+				exponent16 = VF_MAX_F16_EXP;
+				fraction16 = 0;
+			      }
+			    else
+			      { // NaN
+				exponent16 = VF_MAX_F16_EXP;
+				fraction16 = 1;
+			      }
+			  }
+		      }
+		    else
+		      {
+			fraction16 = (f32 &gt;&gt; (VF_SH_F32_EXP - VF_SH_F16_EXP))
+				   &amp; VF_MASK_F16_FRA;
+		      }
+
+		    f16 = (sign &lt;&lt; VF_SH_F16_SIGN)
+			| (exponent16 &lt;&lt; VF_SH_F16_EXP)
+			| (fraction16 &lt;&lt; VF_SH_F16_FRA);
+		    ip-&gt;insn_opcode |= (f16 &amp; VF_MASK_HFLOAT) &lt;&lt; VF_SH_HFLOAT;
+
+		    sprintf(f16_str, "0x%04x", f16);
+		    my_getExpression (&amp;imm_expr, f16_str);
+
+		    continue;
+		  }
+		break;
+
+	      case 'z':	 	/* read/write access code */
+		{
+		  int rwb = 0;
+
+		  if (strncasecmp (s, "WT", 2) == 0)
+		    rwb = 0x0;
+		  else if (strncasecmp (s, "WB", 2) == 0)
+		    rwb = 0x1;
+		  else
+		    as_bad (_("Invalid memory access type (%s)"), s);
+
+		  s += 2;
+		  ip-&gt;insn_opcode |= (rwb &amp; VF_MASK_RWB) &lt;&lt; VF_SH_RWB;
+
+		  continue;
+		}
+
+	      case '0':		/* source or target prefix code (X) */
+	      case '1':		/* source or target prefix code (Y) */
+	      case '2':		/* source or target prefix code (Z) */
+	      case '3':		/* source or target prefix code (W) */
+		{
+		  int operand;
+		  int shift;
+
+		  int pfx_neg = 0;
+		  int pfx_cst = 0;
+		  int pfx_abs = 0;
+		  int pfx_swz = 0;
+		  int pfx_err = 0;
+		  int cst = 0;
+		  char *pfx_str = s;
+
+		  if (s[0] == '-')
+		    {	// sign code
+		      pfx_neg = 1;
+		      s++;
+		    }
+		  
+		  if (ISDIGIT (s[0]))
+		    {	// constant
+		      pfx_cst = 1;
+
+		      if (s[0] == '0')
+			cst = 0;
+		      else if (s[0] == '1')
+			{
+			  if (s[1] == '/')
+			    {
+			      s += 2;
+			      if (s[0] == '2')
+				cst = 3;
+			      else if (s[0] == '3')
+				cst = 5;
+			      else if (s[0] == '4')
+				cst = 6;
+			      else if (s[0] == '6')
+				cst = 7;
+			      else
+				pfx_err = 1;
+			    }
+			  else
+			    {
+			      cst = 1;
+			    }
+			}
+		      else if (s[0] == '2')
+			cst = 2;
+		      else if (s[0] == '3')
+			cst = 4;
+		      else
+			pfx_err = 1;
+
+		      pfx_abs = (cst &gt;&gt; 2) &amp; 0x1;
+		      pfx_swz = (cst &gt;&gt; 0) &amp; 0x3;
+		      s++;
+		    }
+		  else
+		    {  // variable
+		      
+		      if (s[0] == '|')
+			{ // abs
+			  pfx_abs = 1;
+			  s++;
+			}
+		      
+		      if ((s[0] == 'X') || (s[0] == 'x'))
+			{
+			  pfx_swz = 0;
+			  s++;
+			}
+		      else if ((s[0] == 'Y') || (s[0] == 'y'))
+			{
+			  pfx_swz = 1;
+			  s++;
+			}
+		      else if ((s[0] == 'Z') || (s[0] == 'z'))
+			{
+			  pfx_swz = 2;
+			  s++;
+			}
+		      else if ((s[0] == 'W') || (s[0] == 'w'))
+			{
+			  pfx_swz = 3;
+			  s++;
+			}
+		      else if ((s[0] == ',') || IS_SPACE_OR_NUL (s[0])
+			       || (s[0] == '|'))
+			{
+			  pfx_swz =  *args - '0';
+			}
+		      else
+			pfx_err = 1;
+
+		      if (pfx_err == 0)
+			{
+			  if (s[0] == '|')
+			    {
+			      s++;
+			      if (pfx_abs == 0)
+				pfx_err = 1;
+			    }
+			  else
+			    {
+			      if (pfx_abs == 1)
+				pfx_err = 1;
+			    }
+			}
+		    }
+
+		  if (! ((s[0] == ',') || IS_SPACE_OR_NUL (s[0])))
+		    pfx_err = 1;
+
+		  if (pfx_err)
+		    as_bad (_("Invalid prefix format (%s)"), pfx_str);
+
+		  shift = *args - '0';
+
+		  operand = (pfx_neg &lt;&lt; (VF_SH_PFX_NEG + shift))
+			  | (pfx_cst &lt;&lt; (VF_SH_PFX_CST + shift))
+			  | (pfx_abs &lt;&lt; (VF_SH_PFX_ABS + shift))
+			  | (pfx_swz &lt;&lt; (VF_SH_PFX_SWZ + shift * 2));
+
+		  ip-&gt;insn_opcode |= operand;
+		  continue;
+		}
+
+	      case '4':		/* destination prefix code (X) */
+	      case '5':		/* destination prefix code (Y) */
+	      case '6':		/* destination prefix code (Z) */
+	      case '7':		/* destination prefix code (W) */
+		{
+		  int operand;
+		  int shift;
+		  static const char order[] = "xyzwXYZW";
+
+		  int pfx_msk = 0;
+		  int pfx_sat = 0;
+		  char *pfx_str = s;
+
+		  if (s[0] == '[')
+		    s++;
+		  if (s[0] == '-')	/* -1:1, skip the minus symbol */
+		    s++;
+
+		  if ((s[0] == 'm') || (s[0] == 'M'))
+		    {
+		      pfx_msk = 1;
+		      s++;
+		    }
+		  else if (s[0] == '0')	/* 0:1 */
+		    {
+		      pfx_sat = 1;
+		      s++;
+		    }
+		  else if (s[0] == '1')	/* -1:1 or -1:+1 */
+		    {
+		      pfx_sat = 3;
+		      s++;
+		    }
+		  else if ((s[0] == order[(*args) - '4'])
+			   || (s[0] == order[(*args) - '4' + 4]))
+		    {
+		      pfx_sat = 0;
+		      s++;
+		    }
+
+		  if (s[0] == ':')	/* skip the :1 or :+1 part of the expression */
+		    {
+		      s++;
+		      if (s[0] == '+')
+			s++;
+		      if (s[0] == '1')
+			s++;
+		    }
+		  if (s[0] == ']')
+		    s++;
+
+		  if (! ((s[0] == ',') || IS_SPACE_OR_NUL (s[0])))
+		    as_bad (_("Invalid prefix format (%s)"), pfx_str);
+
+		  shift = *args - '4';
+		  operand = (pfx_msk &lt;&lt; (VF_SH_PFX_MSK + shift))
+			  | (pfx_sat &lt;&lt; (VF_SH_PFX_SAT + shift * 2));
+
+		  ip-&gt;insn_opcode |= operand;
+		  continue;
+		}
+	      }
+	      break;
+
+	    case 'b':		/* base register */
+	    case 'd':		/* destination register */
+	    case 's':		/* source register */
+	    case 't':		/* target register */
+	    case 'r':		/* both target and source */
+	    case 'v':		/* both dest and source */
+	    case 'w':		/* both dest and target */
+	    case 'E':		/* coprocessor target register */
+	    case 'G':		/* coprocessor destination register */
+	    case 'K':		/* 'rdhwr' destination register */
+	    case 'x':		/* ignore register name */
+	    case 'z':		/* must be zero register */
+	    case 'U':           /* destination register (clo/clz).  */
+	      s_reset = s;
+	      if (s[0] == '$')
+		{
+
+		  if (ISDIGIT (s[1]))
+		    {
+		      ++s;
 		      regno = 0;
 		      do
 			{
@@ -8273,30 +9967,27 @@
 		    goto notreg;
 		  else
 		    {
-		      if (s[1] == 'r' &amp;&amp; s[2] == 'a')
+				const char regName[32][5] =
 			{
-			  s += 3;
-			  regno = RA;
-			}
-		      else if (s[1] == 'f' &amp;&amp; s[2] == 'p')
+					"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
+					"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 
+					"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+					"t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra"
+				};
+				int i;
+
+				for(i = 0; i &lt; 32; i++)
 			{
-			  s += 3;
-			  regno = FP;
-			}
-		      else if (s[1] == 's' &amp;&amp; s[2] == 'p')
+					if(strncmp(&amp;s[1], regName[i], strlen(regName[i])) == 0)
 			{
-			  s += 3;
-			  regno = SP;
+						break;
 			}
-		      else if (s[1] == 'g' &amp;&amp; s[2] == 'p')
-			{
-			  s += 3;
-			  regno = GP;
 			}
-		      else if (s[1] == 'a' &amp;&amp; s[2] == 't')
+
+				if(i &lt; 32)
 			{
-			  s += 3;
-			  regno = AT;
+					s += strlen(regName[i]) + 1;
+					regno = i;
 			}
 		      else if (s[1] == 'k' &amp;&amp; s[2] == 't' &amp;&amp; s[3] == '0')
 			{
@@ -8485,6 +10176,7 @@
 
 		  if ((regno &amp; 1) != 0
 		      &amp;&amp; HAVE_32BIT_FPRS
+		      &amp;&amp; ! CPU_IS_ALLEGREX (mips_opts.arch)
 		      &amp;&amp; ! (strcmp (str, "mtc1") == 0
 			    || strcmp (str, "mfc1") == 0
 			    || strcmp (str, "lwc1") == 0
@@ -13743,6 +15435,8 @@
 
   /* MIPS II */
   { "r6000",          0,      ISA_MIPS2,      CPU_R6000 },
+  /* Sony PSP "Allegrex" CPU core */
+  { "allegrex",       0,      ISA_MIPS2,      CPU_ALLEGREX },
 
   /* MIPS III */
   { "r4000",          0,      ISA_MIPS3,      CPU_R4000 },
diff -burN binutils-2.16.1/gas/configure binutils-psp/gas/configure
--- binutils-2.16.1/gas/configure	2005-03-01 00:43:51.000000000 +0000
+++ binutils-psp/gas/configure	2006-05-09 02:55:36.000000000 +0100
@@ -4537,6 +4537,9 @@
 	  mips64vr | mips64vrel)
 	    mips_cpu=vr4100
 	    ;;
+	  mipsallegrex | mipsallegrexel)
+	    mips_cpu=allegrex
+	    ;;
 	  mipsisa32r2* | mipsisa64r2*)
 	    mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'`
 	    ;;
diff -burN binutils-2.16.1/gas/configure.in binutils-psp/gas/configure.in
--- binutils-2.16.1/gas/configure.in	2005-03-01 00:43:57.000000000 +0000
+++ binutils-psp/gas/configure.in	2006-05-09 02:55:36.000000000 +0100
@@ -222,6 +222,9 @@
 	  mips64vr | mips64vrel)
 	    mips_cpu=vr4100
 	    ;;
+	  mipsallegrex | mipsallegrexel)
+	    mips_cpu=allegrex
+	    ;;
 	  mipsisa32r2* | mipsisa64r2*)
 changequote(,)dnl
 	    mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'`
diff -burN binutils-2.16.1/gas/testsuite/gas/mips/mips.exp binutils-psp/gas/testsuite/gas/mips/mips.exp
--- binutils-2.16.1/gas/testsuite/gas/mips/mips.exp	2005-04-19 18:09:45.000000000 +0100
+++ binutils-psp/gas/testsuite/gas/mips/mips.exp	2006-05-09 02:55:36.000000000 +0100
@@ -382,6 +382,9 @@
 mips_arch_create sb1 	64	mips64	{ mips3d } \
 			{ -march=sb1 -mtune=sb1 } { -mmips:sb1 } \
 			{ mipsisa64sb1-*-* mipsisa64sb1el-*-* }
+mips_arch_create allegrex 32	mips2	{ ror } \
+			{ -march=allegrex -mtune=allegrex } { -mmips:allegrex } \
+			{ mipsallegrex-*-* mipsallegrexel-*-* }
 
 
 #
diff -burN binutils-2.16.1/include/bin-bugs.h binutils-psp/include/bin-bugs.h
--- binutils-2.16.1/include/bin-bugs.h	2004-07-23 16:40:19.000000000 +0100
+++ binutils-psp/include/bin-bugs.h	2006-05-09 02:55:36.000000000 +0100
@@ -1,3 +1,3 @@
 #ifndef REPORT_BUGS_TO
-#define REPORT_BUGS_TO	"&lt;URL:http://www.sourceware.org/bugzilla/&gt;"
+#define REPORT_BUGS_TO	"&lt;URL:http://wiki.pspdev.org/psp:toolchain#bugs&gt;"
 #endif
diff -burN binutils-2.16.1/include/elf/common.h binutils-psp/include/elf/common.h
--- binutils-2.16.1/include/elf/common.h	2004-10-08 14:55:08.000000000 +0100
+++ binutils-psp/include/elf/common.h	2006-05-09 02:55:36.000000000 +0100
@@ -93,6 +93,7 @@
 #define ET_HIOS		0xFEFF	/* Operating system-specific */
 #define ET_LOPROC	0xFF00	/* Processor-specific */
 #define ET_HIPROC	0xFFFF	/* Processor-specific */
+#define ET_PSPEXEC	0xFFA0	/* Sony PSP executable file */
 
 /* Values for e_machine, which identifies the architecture.  These numbers
    are officially assigned by registry@caldera.com.  See below for a list of
diff -burN binutils-2.16.1/include/elf/mips.h binutils-psp/include/elf/mips.h
--- binutils-2.16.1/include/elf/mips.h	2005-03-03 11:58:06.000000000 +0000
+++ binutils-psp/include/elf/mips.h	2006-05-09 02:55:36.000000000 +0100
@@ -212,6 +212,7 @@
 #define E_MIPS_MACH_5400	0x00910000
 #define E_MIPS_MACH_5500	0x00980000
 #define E_MIPS_MACH_9000	0x00990000
+#define E_MIPS_MACH_ALLEGREX	0x00A20000
 
 /* Processor specific section indices.  These sections do not actually
    exist.  Symbols with a st_shndx field corresponding to one of these
diff -burN binutils-2.16.1/include/opcode/mips.h binutils-psp/include/opcode/mips.h
--- binutils-2.16.1/include/opcode/mips.h	2005-03-03 11:58:10.000000000 +0000
+++ binutils-psp/include/opcode/mips.h	2006-05-09 02:55:36.000000000 +0100
@@ -171,6 +171,228 @@
 #define MDMX_FMTSEL_VEC_QH	0x15
 #define MDMX_FMTSEL_VEC_OB	0x16
 
+#include "vfpu.h"
+
+#define VF_MASK_VT		0x7f
+#define VF_SH_VT		16
+#define VF_MASK_VS		0x7f
+#define VF_SH_VS		8
+#define VF_MASK_VD		0x7f
+#define VF_SH_VD		0
+#define VF_MASK_VML		0x1f
+#define VF_SH_VML		16
+#define VF_MASK_VMH		0x3
+#define VF_SH_VMH		0
+#define VF_MASK_VNL		0x1f
+#define VF_SH_VNL		16
+#define VF_MASK_VNH		0x1
+#define VF_SH_VNH		0
+#define VF_MASK_OFFSET		0x3fff
+#define VF_SH_OFFSET		2
+#define VF_MASK_CC		0xf
+#define VF_SH_CC		0
+#define VF_MASK_CONST		0x1f
+#define VF_SH_CONST		16
+#define VF_MASK_SCALE		0x1f
+#define VF_SH_SCALE		16
+#define VF_MASK_BCOND		0x7
+#define VF_SH_BCOND		18
+#define VF_MASK_MCOND		0x7
+#define VF_SH_MCOND		16
+#define VF_MASK_VCD		0xff
+#define VF_SH_VCD		0
+#define VF_MASK_VCS		0xff
+#define VF_SH_VCS		8
+#define VF_MASK_ROT		0x1f
+#define VF_SH_ROT		16
+#define VF_MASK_WRAP		0xff
+#define VF_SH_WRAP		16
+#define VF_MASK_TSIGN		0x1
+#define VF_SH_TSIGN		5
+#define VF_MASK_BMCOND		0x1f
+#define VF_SH_BMCOND		0
+#define VF_MASK_HFLOAT		0xffff
+#define VF_SH_HFLOAT		0
+#define VF_MASK_PFX		0xffffff
+#define VF_SH_PFX		0
+#define VF_MASK_RWB		0x1
+#define VF_SH_RWB		1
+
+#define	VF_MASK_PFX_SWZ		0x3
+#define	VF_SH_PFX_SWZ		0
+#define	VF_MASK_PFX_ABS		0x1
+#define	VF_SH_PFX_ABS		8
+#define	VF_MASK_PFX_CST		0x1
+#define	VF_SH_PFX_CST		12
+#define	VF_MASK_PFX_NEG		0x1
+#define	VF_SH_PFX_NEG		16
+#define	VF_MASK_PFX_SAT		0x3
+#define	VF_SH_PFX_SAT		0
+#define	VF_MASK_PFX_MSK		0x1
+#define	VF_SH_PFX_MSK		8
+
+#define	VF_MASK_ROT_COS		0x3
+#define	VF_SH_ROT_COS		0
+#define	VF_MASK_ROT_SIN		0x3
+#define	VF_SH_ROT_SIN		2
+#define	VF_MASK_ROT_NEG		0x1
+#define	VF_SH_ROT_NEG		4
+
+#define	VF_MASK_MR_MTX		0x7
+#define	VF_SH_MR_MTX		2
+#define	VF_MASK_MR_IDX		0x3
+#define	VF_SH_MR_IDX		0
+#define	VF_MASK_MR_FSL		0x3
+#define	VF_SH_MR_FSL		5
+#define	VF_MASK_MR_RXC		0x1
+#define	VF_SH_MR_RXC		5
+#define	VF_MASK_MR_VFSL		0x1
+#define	VF_SH_MR_VFSL		6
+
+#define	VF_MAX_MR_MTX		7
+#define	VF_MAX_MR_IDX		3
+#define	VF_MAX_MR_FSL		3
+#define	VF_MAX_MR_VIDX		1
+#define	VF_MAX_MR_VFSL		1
+
+#define	VF_MIN_MR		0
+#define	VF_MAX_MR		127
+#define	VF_MIN_CR		128
+#define	VF_MAX_CR		255
+#define	VF_MIN_VCR		128
+#define	VF_MAX_VCR		143
+#define	VF_MIN_CC		0
+#define	VF_MAX_CC		15
+#define	VF_MIN_CONST		1
+#define	VF_MAX_CONST		19
+#define	VF_MIN_SCALE		0
+#define	VF_MAX_SCALE		31
+#define	VF_MIN_BCOND		0
+#define	VF_MAX_BCOND		5
+#define	VF_MIN_MCOND		0
+#define	VF_MAX_MCOND		6
+#define	VF_MIN_WRAP		0
+#define	VF_MAX_WRAP		255
+#define	VF_MIN_ROT		0
+#define	VF_MAX_ROT		31
+#define	VF_MIN_TSIGN		0
+#define	VF_MAX_TSIGN		1
+#define	VF_MIN_BMCOND		0
+#define	VF_MAX_BMCOND		31
+#define	VF_MIN_HFLOAT		0
+#define	VF_MAX_HFLOAT		0xffff
+
+#define	VF_MASK_F32_SIGN	0x1
+#define	VF_SH_F32_SIGN		31
+#define	VF_MASK_F32_EXP		0xff
+#define	VF_SH_F32_EXP		23
+#define	VF_MASK_F32_FRA		0x7fffff
+#define	VF_SH_F32_FRA		0
+#define	VF_MASK_F16_SIGN	0x1
+#define	VF_SH_F16_SIGN		15
+#define	VF_MASK_F16_EXP		0x1f
+#define	VF_SH_F16_EXP		10
+#define	VF_MASK_F16_FRA		0x3ff
+#define	VF_SH_F16_FRA		0
+
+#define	VF_MIN_F32_EXP		0
+#define	VF_MAX_F32_EXP		255
+#define	VF_BIAS_F32_EXP		127
+#define	VF_MIN_F16_EXP		0
+#define	VF_MAX_F16_EXP		31
+#define	VF_BIAS_F16_EXP		15
+
+#define OP_SH_VFPU_DELTA	0
+#define OP_MASK_VFPU_DELTA	0xfffc
+#define OP_SH_VFPU_IMM3		16
+#define OP_MASK_VFPU_IMM3	0x7
+#define OP_SH_VFPU_IMM5		16
+#define OP_MASK_VFPU_IMM5	0x1f
+#define OP_SH_VFPU_IMM8		16
+#define OP_MASK_VFPU_IMM8	0xff
+#define OP_SH_VFPU_CC		18	/* Condition code. */
+#define OP_MASK_VFPU_CC		0x7
+#define OP_SH_VFPU_CONST	16
+#define OP_MASK_VFPU_CONST	0x1f
+#define OP_SH_VFPU_COND		0	/* Conditional compare. */
+#define OP_MASK_VFPU_COND	0xf
+#define OP_SH_VFPU_VMTVC	0
+#define OP_MASK_VFPU_VMTVC	0xff
+#define OP_SH_VFPU_VMFVC	8
+#define OP_MASK_VFPU_VMFVC	0xff
+#define OP_SH_VFPU_RWB		1
+#define OP_MASK_VFPU_RWB	0x1
+#define OP_SH_VFPU_ROT		16	/* Rotators used in vrot. */
+#define OP_MASK_VFPU_ROT	0x1f
+#define OP_SH_VFPU_FLOAT16	0
+#define OP_MASK_VFPU_FLOAT16	0xffff
+
+/* VFPU registers. */
+#define OP_SH_VFPU_VD		0
+#define OP_MASK_VFPU_VD		0x7f
+#define OP_SH_VFPU_VS		8
+#define OP_MASK_VFPU_VS		0x7f
+#define OP_SH_VFPU_VT		16
+#define OP_MASK_VFPU_VT		0x7f
+#define OP_SH_VFPU_VT_LO	16	/* Bits 0-4 of vt. */
+#define OP_MASK_VFPU_VT_LO	0x1f
+#define OP_SH_VFPU_VT_HI	5	/* Right-shifted. */
+#define OP_MASK_VFPU_VT_HI1	0x1	/* Bit 5 of vt. */
+#define OP_MASK_VFPU_VT_HI2	0x3	/* Bits 5-6 of vt. */
+/* Special handling of vs in vmmul instructions. */
+#define VFPU_OP_VT_VS_VD	0xff800000
+#define VFPU_OPCODE_VMMUL	0xf0000000
+
+/* VFPU condition codes.  FL and TR accept no arguments, while any conditions
+   above and including EZ only accept one argument.  The rest require two
+   arguments.  */
+enum
+{
+  VFPU_COND_FL, VFPU_COND_EQ, VFPU_COND_LT, VFPU_COND_LE,
+  VFPU_COND_TR, VFPU_COND_NE, VFPU_COND_GE, VFPU_COND_GT,
+  VFPU_COND_EZ, VFPU_COND_EN, VFPU_COND_EI, VFPU_COND_ES,
+  VFPU_COND_NZ, VFPU_COND_NN, VFPU_COND_NI, VFPU_COND_NS,
+  VFPU_NUM_CONDS
+};
+
+/* VFPU prefix instruction operands.  The *_SH_* values really specify where
+   the bitfield begins, as VFPU prefix instructions have four operands
+   encoded within the immediate field. */
+#define VFPU_SH_PFX_NEG		16
+#define VFPU_MASK_PFX_NEG	0x1	/* Negation. */
+#define VFPU_SH_PFX_CST		12
+#define VFPU_MASK_PFX_CST	0x1	/* Constant. */
+#define VFPU_SH_PFX_ABS_CSTHI	8
+#define VFPU_MASK_PFX_ABS_CSTHI	0x1	/* Abs/Constant (bit 2). */
+#define VFPU_SH_PFX_SWZ_CSTLO	0
+#define VFPU_MASK_PFX_SWZ_CSTLO	0x3	/* Swizzle/Constant (bits 0-1). */
+#define VFPU_SH_PFX_MASK	8
+#define VFPU_MASK_PFX_MASK	0x1	/* Mask. */
+#define VFPU_SH_PFX_SAT		0
+#define VFPU_MASK_PFX_SAT	0x3	/* Saturation. */
+
+/* Special handling of the vrot instructions. */
+#define VFPU_MASK_OP_SIZE	0x8080	/* Masks the operand size (pair, triple, quad). */
+#define VFPU_OP_SIZE_PAIR	0x80
+#define VFPU_OP_SIZE_TRIPLE	0x8000
+#define VFPU_OP_SIZE_QUAD	0x8080
+/* Note that these are within the rotators field, and not the full opcode. */
+#define VFPU_SH_ROT_HI		2
+#define VFPU_MASK_ROT_HI	0x3
+#define VFPU_SH_ROT_LO		0
+#define VFPU_MASK_ROT_LO	0x3
+#define VFPU_SH_ROT_NEG		4	/* Negation. */
+#define VFPU_MASK_ROT_NEG	0x1
+
+/* VFPU 16-bit floating-point format. */
+#define VFPU_FLOAT16_EXP_MAX	0x1f
+#define VFPU_SH_FLOAT16_SIGN	15
+#define VFPU_MASK_FLOAT16_SIGN	0x1
+#define VFPU_SH_FLOAT16_EXP	10
+#define VFPU_MASK_FLOAT16_EXP	0x1f
+#define VFPU_SH_FLOAT16_FRAC	0
+#define VFPU_MASK_FLOAT16_FRAC	0x3ff
+
 /* This structure holds information for a particular instruction.  */
 
 struct mips_opcode
@@ -258,6 +480,29 @@
 	Requires that "+A" or "+E" occur first to set position.
 	Enforces: 32 &lt; (pos+size) &lt;= 64.
 
+   Sony Allegrex VFPU instructions:
+   "?o"
+   "?0" - "?3"
+   "?4" - "?7"
+   "?a"
+   "?b"
+   "?c"
+   "?e"
+   "?f"
+   "?i"
+   "?q"
+   "?r"
+   "?u"
+   "?w"
+   "?d"
+   "?m"
+   "?n"
+   "?s"
+   "?t"
+   "?v"
+   "?x"
+   "?z"
+
    Floating point instructions:
    "D" 5 bit destination register (OP_*_FD)
    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
@@ -442,6 +687,8 @@
 #define INSN_5400		  0x01000000
 /* NEC VR5500 instruction.  */
 #define INSN_5500		  0x02000000
+/* Sony Allegrex instruction.  */
+#define INSN_ALLEGREX		  0x10000000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -489,6 +736,7 @@
 #define CPU_MIPS64      64
 #define CPU_MIPS64R2	65
 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
+#define CPU_ALLEGREX    10111431        /* octal 'AL', 31.  */
 
 /* Test for membership in an ISA including chip specific ISAs.  INSN
    is pointer to an element of the opcode table; ISA is the specified
@@ -510,6 +758,7 @@
      || (cpu == CPU_VR4120 &amp;&amp; ((insn)-&gt;membership &amp; INSN_4120) != 0)	\
      || (cpu == CPU_VR5400 &amp;&amp; ((insn)-&gt;membership &amp; INSN_5400) != 0)	\
      || (cpu == CPU_VR5500 &amp;&amp; ((insn)-&gt;membership &amp; INSN_5500) != 0)	\
+     || (cpu == CPU_ALLEGREX &amp;&amp; ((insn)-&gt;membership &amp; INSN_ALLEGREX) != 0)	\
      || 0)	/* Please keep this term for easier source merging.  */
 
 /* This is a list of macro expanded instructions.
@@ -622,9 +871,25 @@
   M_LI_DD,
   M_LI_S,
   M_LI_SS,
+  M_LVHI_S_SS,
+  M_LVHI_P_SS,
+  M_LVI_S_SS,
+  M_LVI_P_SS,
+  M_LVI_T_SS,
+  M_LVI_Q_SS,
   M_LL_AB,
   M_LLD_AB,
   M_LS_A,
+  M_LVHI_P,
+  M_LVHI_S,
+  M_LVI_P,
+  M_LVI_Q,
+  M_LVI_S,
+  M_LVI_T,
+  M_LVL_Q_AB,
+  M_LVR_Q_AB,
+  M_LV_Q_AB,
+  M_LV_Q_AB_2,
   M_LW_A,
   M_LW_AB,
   M_LWC0_A,
@@ -635,6 +900,7 @@
   M_LWC2_AB,
   M_LWC3_A,
   M_LWC3_AB,
+  M_LV_S_AB,
   M_LWL_A,
   M_LWL_AB,
   M_LWR_A,
@@ -714,6 +980,10 @@
   M_SUB_I,
   M_SUBU_I,
   M_SUBU_I_2,
+  M_SVL_Q_AB,
+  M_SV_Q_AB,
+  M_SVR_Q_AB,
+  M_SV_S_AB,
   M_TEQ_I,
   M_TGE_I,
   M_TGEU_I,
@@ -728,14 +998,24 @@
   M_ULH_A,
   M_ULHU,
   M_ULHU_A,
+  M_ULV_Q,
+  M_ULV_Q_AB,
+  M_ULV_S,
   M_ULW,
   M_ULW_A,
   M_USH,
   M_USH_A,
+  M_USV_Q,
+  M_USV_Q_AB,
+  M_USV_S,
   M_USW,
   M_USW_A,
   M_USD,
   M_USD_A,
+  M_VCMOV_P,
+  M_VCMOV_Q,
+  M_VCMOV_S,
+  M_VCMOV_T,
   M_XOR_I,
   M_COP0,
   M_COP1,
diff -burN binutils-2.16.1/include/opcode/vfpu.h binutils-psp/include/opcode/vfpu.h
--- binutils-2.16.1/include/opcode/vfpu.h	1970-01-01 01:00:00.000000000 +0100
+++ binutils-psp/include/opcode/vfpu.h	2006-05-09 02:55:36.000000000 +0100
@@ -0,0 +1,261 @@
+#ifndef _VFPU_H_
+#define _VFPU_H_
+
+////////////////////////////////////
+// data type
+#define VFPU_MASK_DTYPE		0x8080
+#define VFPU_QUAD		0x8080
+#define VFPU_TRIPLE		0x8000
+#define VFPU_PAIR		0x0080
+#define VFPU_SINGLE		0x0000
+
+////////////////////////////////////
+// register index
+#define VFPU_MASK_VT		0x7f0000
+#define VFPU_MASK_VS		0x007f00
+#define VFPU_MASK_VD		0x00007f
+
+////////////////////////////////////
+// condition and comapre inst
+#define VFPU_PADD_BIN_CMP	0x70
+
+////////////////////////////////////
+// load/store left/right
+#define VFPU_MASK_LDST_LR	0x2
+#define VFPU_LDST_L		0x0
+#define VFPU_LDST_R		0x2
+
+////////////////////////////////////
+// load/store memory/buffer
+#define VFPU_MASK_LDST_MB	0x2
+#define VFPU_LDST_M		0x0
+#define VFPU_LDST_B		0x2
+
+////////////////////////////////////
+// coprocessor move
+#define VFPU_MASK_COP_MV	0xff80
+#define VFPU_MASK_COP_MVC	0xff00
+
+////////////////////////////////////
+// sync code
+#define	VFPU_MASK_SYNC_CODE	0xffff
+#define	VFPU_SYNC_CODE_DEFAULT	0x0320
+#define	VFPU_SYNC_CODE_NOP	0x0000
+#define	VFPU_SYNC_CODE_FLUSH	0x040d
+
+////////////////////////////////////
+#define VFPU_INST_BR_F	 	0x49000000
+#define VFPU_MASK_BR_F	 	0xffe30000
+#define VFPU_INST_BR_FL	 	0x49020000
+#define VFPU_MASK_BR_FL	 	0xffe30000
+#define VFPU_INST_BR_T	 	0x49010000
+#define VFPU_MASK_BR_T	 	0xffe30000
+#define VFPU_INST_BR_TL	 	0x49030000
+#define VFPU_MASK_BR_TL	 	0xffe30000
+
+#define VFPU_INST_COP_LD_S 	0xc8000000
+#define VFPU_MASK_COP_LD_S 	0xfc000000
+#define VFPU_INST_COP_ST_S 	0xe8000000
+#define VFPU_MASK_COP_ST_S 	0xfc000000
+#define VFPU_INST_COP_LD_Q 	0xd8000000
+#define VFPU_MASK_COP_LD_Q 	0xfc000000
+#define VFPU_INST_COP_ST_Q 	0xf8000000
+#define VFPU_MASK_COP_ST_Q 	0xfc000000
+#define VFPU_INST_COP_LD_U 	0xd4000000
+#define VFPU_MASK_COP_LD_U 	0xfc000000
+#define VFPU_INST_COP_ST_U 	0xf4000000
+#define VFPU_MASK_COP_ST_U 	0xfc000000
+#define VFPU_INST_COP_MF 	0x48600000
+#define VFPU_MASK_COP_MF 	0xffe00000
+#define VFPU_INST_COP_MT 	0x48e00000
+#define VFPU_MASK_COP_MT 	0xffe00000
+
+#define VFPU_INST_BIN_ADD 	0x60000000
+#define VFPU_MASK_BIN_ADD 	0xff800000
+#define VFPU_INST_BIN_SUB 	0x60800000
+#define VFPU_MASK_BIN_SUB 	0xff800000
+#define VFPU_INST_BIN_SBN 	0x61000000
+#define VFPU_MASK_BIN_SBN 	0xff800000
+#define VFPU_INST_BIN_DIV 	0x63800000
+#define VFPU_MASK_BIN_DIV 	0xff800000
+#define VFPU_INST_BIN_MUL 	0x64000000
+#define VFPU_MASK_BIN_MUL 	0xff800000
+#define VFPU_INST_BIN_DOT 	0x64800000
+#define VFPU_MASK_BIN_DOT 	0xff800000
+#define VFPU_INST_BIN_SCL 	0x65000000
+#define VFPU_MASK_BIN_SCL 	0xff800000
+#define VFPU_INST_BIN_HDP 	0x66000000
+#define VFPU_MASK_BIN_HDP 	0xff800000
+#define VFPU_INST_BIN_CRS 	0x66800000
+#define VFPU_MASK_BIN_CRS 	0xff800000
+#define VFPU_INST_BIN_DET 	0x67000000
+#define VFPU_MASK_BIN_DET 	0xff800000
+#define VFPU_INST_BIN_CMP 	0x6c000000
+#define VFPU_MASK_BIN_CMP 	0xff800000
+#define VFPU_INST_BIN_MIN 	0x6d000000
+#define VFPU_MASK_BIN_MIN 	0xff800000
+#define VFPU_INST_BIN_MAX 	0x6d800000
+#define VFPU_MASK_BIN_MAX 	0xff800000
+#define VFPU_INST_BIN_SCMP 	0x6e800000
+#define VFPU_MASK_BIN_SCMP 	0xff800000
+#define VFPU_INST_BIN_SGE 	0x6f000000
+#define VFPU_MASK_BIN_SGE 	0xff800000
+#define VFPU_INST_BIN_SLT 	0x6f800000
+#define VFPU_MASK_BIN_SLT 	0xff800000
+
+#define VFPU_INST_UNR_MOV 	0xd0000000
+#define VFPU_MASK_UNR_MOV 	0xffff0000
+#define VFPU_INST_UNR_ABS 	0xd0010000
+#define VFPU_MASK_UNR_ABS 	0xffff0000
+#define VFPU_INST_UNR_NEG 	0xd0020000
+#define VFPU_MASK_UNR_NEG 	0xffff0000
+#define VFPU_INST_UNR_IDT 	0xd0030000
+#define VFPU_MASK_UNR_IDT 	0xffff0000
+#define VFPU_INST_UNR_SAT0 	0xd0040000
+#define VFPU_MASK_UNR_SAT0 	0xffff0000
+#define VFPU_INST_UNR_SAT1 	0xd0050000
+#define VFPU_MASK_UNR_SAT1 	0xffff0000
+#define VFPU_INST_UNR_ZERO 	0xd0060000
+#define VFPU_MASK_UNR_ZERO 	0xffff0000
+#define VFPU_INST_UNR_ONE 	0xd0070000
+#define VFPU_MASK_UNR_ONE 	0xffff0000
+#define VFPU_INST_UNR_RCP 	0xd0100000
+#define VFPU_MASK_UNR_RCP 	0xffff0000
+#define VFPU_INST_UNR_RSQ 	0xd0110000
+#define VFPU_MASK_UNR_RSQ 	0xffff0000
+#define VFPU_INST_UNR_SIN 	0xd0120000
+#define VFPU_MASK_UNR_SIN 	0xffff0000
+#define VFPU_INST_UNR_COS 	0xd0130000
+#define VFPU_MASK_UNR_COS 	0xffff0000
+#define VFPU_INST_UNR_EXP2 	0xd0140000
+#define VFPU_MASK_UNR_EXP2 	0xffff0000
+#define VFPU_INST_UNR_LOG2 	0xd0150000
+#define VFPU_MASK_UNR_LOG2 	0xffff0000
+#define VFPU_INST_UNR_SQR 	0xd0160000
+#define VFPU_MASK_UNR_SQR 	0xffff0000
+#define VFPU_INST_UNR_ASIN 	0xd0170000
+#define VFPU_MASK_UNR_ASIN 	0xffff0000
+#define VFPU_INST_UNR_NRCP 	0xd0180000
+#define VFPU_MASK_UNR_NRCP 	0xffff0000
+#define VFPU_INST_UNR_NSIN 	0xd01a0000
+#define VFPU_MASK_UNR_NSIN 	0xffff0000
+#define VFPU_INST_UNR_REXP2 	0xd01c0000
+#define VFPU_MASK_UNR_REXP2 	0xffff0000
+#define VFPU_INST_UNR_RNDS 	0xd0200000
+#define VFPU_MASK_UNR_RNDS 	0xffff0000
+#define VFPU_INST_UNR_RNDI 	0xd0210000
+#define VFPU_MASK_UNR_RNDI 	0xffff0000
+#define VFPU_INST_UNR_RNDF1 	0xd0220000
+#define VFPU_MASK_UNR_RNDF1 	0xffff0000
+#define VFPU_INST_UNR_RNDF2 	0xd0230000
+#define VFPU_MASK_UNR_RNDF2 	0xffff0000
+#define VFPU_INST_UNR_F2H 	0xd0320000
+#define VFPU_MASK_UNR_F2H 	0xffff0000
+#define VFPU_INST_UNR_H2F 	0xd0330000
+#define VFPU_MASK_UNR_H2F 	0xffff0000
+#define VFPU_INST_UNR_SBZ 	0xd0360000
+#define VFPU_MASK_UNR_SBZ 	0xffff0000
+#define VFPU_INST_UNR_LGB 	0xd0370000
+#define VFPU_MASK_UNR_LGB 	0xffff0000
+#define	VFPU_INST_UNR_US2I	0xd03a0000
+#define	VFPU_MASK_UNR_US2I	0xffff0000
+#define	VFPU_INST_UNR_S2I	0xd03b0000
+#define	VFPU_MASK_UNR_S2I	0xffff0000
+#define	VFPU_INST_UNR_I2UC	0xd03c0000
+#define	VFPU_MASK_UNR_I2UC	0xffff0000
+#define	VFPU_INST_UNR_I2C	0xd03d0000
+#define	VFPU_MASK_UNR_I2C	0xffff0000
+#define	VFPU_INST_UNR_I2US	0xd03e0000
+#define	VFPU_MASK_UNR_I2US	0xffff0000
+#define	VFPU_INST_UNR_I2S	0xd03f0000
+#define	VFPU_MASK_UNR_I2S	0xffff0000
+#define VFPU_INST_UNR_SRT1 	0xd0400000
+#define VFPU_MASK_UNR_SRT1 	0xffff0000
+#define VFPU_INST_UNR_SRT2 	0xd0410000
+#define VFPU_MASK_UNR_SRT2 	0xffff0000
+#define VFPU_INST_UNR_BFY1 	0xd0420000
+#define VFPU_MASK_UNR_BFY1 	0xffff0000
+#define VFPU_INST_UNR_BFY2 	0xd0430000
+#define VFPU_MASK_UNR_BFY2 	0xffff0000
+#define VFPU_INST_UNR_OCP 	0xd0440000
+#define VFPU_MASK_UNR_OCP 	0xffff0000
+#define VFPU_INST_UNR_SOCP 	0xd0450000
+#define VFPU_MASK_UNR_SOCP 	0xffff0000
+#define VFPU_INST_UNR_FAD 	0xd0460000
+#define VFPU_MASK_UNR_FAD 	0xffff0000
+#define VFPU_INST_UNR_AVG 	0xd0470000
+#define VFPU_MASK_UNR_AVG 	0xffff0000
+#define VFPU_INST_UNR_SRT3 	0xd0480000
+#define VFPU_MASK_UNR_SRT3 	0xffff0000
+#define VFPU_INST_UNR_SRT4 	0xd0490000
+#define VFPU_MASK_UNR_SRT4 	0xffff0000
+#define VFPU_INST_UNR_SGN 	0xd04a0000
+#define VFPU_MASK_UNR_SGN 	0xffff0000
+#define VFPU_INST_UNR_CF 	0xd0500000
+#define VFPU_MASK_UNR_CF 	0xffff0080
+#define VFPU_INST_UNR_CT 	0xd0510000
+#define VFPU_MASK_UNR_CT 	0xffff8000
+#define VFPU_INST_UNR_T4444 	0xd0590000
+#define VFPU_MASK_UNR_T4444 	0xffff0000
+#define VFPU_INST_UNR_T5551 	0xd05a0000
+#define VFPU_MASK_UNR_T5551 	0xffff0000
+#define VFPU_INST_UNR_T5650 	0xd05b0000
+#define VFPU_MASK_UNR_T5650 	0xffff0000
+#define VFPU_INST_UNR_CST 	0xd0600000
+#define VFPU_MASK_UNR_CST 	0xffe00000
+
+#define VFPU_INST_UNRI_F2I_N 	0xd2000000
+#define VFPU_MASK_UNRI_F2I_N 	0xffe00000
+#define VFPU_INST_UNRI_F2I_Z 	0xd2200000
+#define VFPU_MASK_UNRI_F2I_Z 	0xffe00000
+#define VFPU_INST_UNRI_F2I_U 	0xd2400000
+#define VFPU_MASK_UNRI_F2I_U 	0xffe00000
+#define VFPU_INST_UNRI_F2I_D 	0xd2600000
+#define VFPU_MASK_UNRI_F2I_D 	0xffe00000
+#define VFPU_INST_UNRI_I2F 	0xd2800000
+#define VFPU_MASK_UNRI_I2F 	0xffe00000
+#define VFPU_INST_UNRI_CMOV_T 	0xd2a00000
+#define VFPU_MASK_UNRI_CMOV_T	0xfff80000
+#define VFPU_INST_UNRI_CMOV_F 	0xd2a80000
+#define VFPU_MASK_UNRI_CMOV_F	0xfff80000
+#define VFPU_INST_UNRI_WBN 	0xd3000000
+#define VFPU_MASK_UNRI_WBN 	0xff000000
+
+#define VFPU_INST_PFX_RA 	0xdc000000
+#define VFPU_MASK_PFX_RA 	0xff000000
+#define VFPU_INST_PFX_RB 	0xdd000000
+#define VFPU_MASK_PFX_RB 	0xff000000
+#define VFPU_INST_PFX_W 	0xde000000
+#define VFPU_MASK_PFX_W 	0xff000000
+#define VFPU_INST_IIM	 	0xdf000000
+#define VFPU_MASK_IIM	 	0xff800000
+#define VFPU_INST_FIM	 	0xdf800000
+#define VFPU_MASK_FIM	 	0xff800000
+
+#define VFPU_INST_RPT_MMUL 	0xf0000000
+#define VFPU_MASK_RPT_MMUL 	0xff800000
+#define VFPU_INST_RPT_TFM2 	0xf0800000
+#define VFPU_MASK_RPT_TFM2 	0xff800000
+#define VFPU_INST_RPT_TFM3 	0xf1000000
+#define VFPU_MASK_RPT_TFM3 	0xff800000
+#define VFPU_INST_RPT_TFM4 	0xf1800000
+#define VFPU_MASK_RPT_TFM4 	0xff800000
+#define VFPU_INST_RPT_MSCL 	0xf2000000
+#define VFPU_MASK_RPT_MSCL 	0xff800000
+#define VFPU_INST_RPT_QMUL 	0xf2800000
+#define VFPU_MASK_RPT_QMUL 	0xff800000
+#define VFPU_INST_RPT_MMOV 	0xf3800000
+#define VFPU_MASK_RPT_MMOV 	0xffff0000
+#define VFPU_INST_RPT_MIDT 	0xf3830000
+#define VFPU_MASK_RPT_MIDT 	0xffff0000
+#define VFPU_INST_RPT_MZERO 	0xf3860000
+#define VFPU_MASK_RPT_MZERO 	0xffff0000
+#define VFPU_INST_RPT_MONE 	0xf3870000
+#define VFPU_MASK_RPT_MONE 	0xffff0000
+#define VFPU_INST_RPT_ROT 	0xf3a00000
+#define VFPU_MASK_RPT_ROT 	0xffe00000
+
+#define VFPU_INST_SYNC		0xffff0000
+#define VFPU_MASK_SYNC		0xffff0000
+
+#endif /* _VFPU_H_ */
diff -burN binutils-2.16.1/ld/configure.tgt binutils-psp/ld/configure.tgt
--- binutils-2.16.1/ld/configure.tgt	2005-02-08 19:54:27.000000000 +0000
+++ binutils-psp/ld/configure.tgt	2006-05-09 02:55:36.000000000 +0100
@@ -428,6 +428,8 @@
 mips*vr4100-*-elf*)	targ_emul=elf32b4300 ;;
 mips*vr5000el-*-elf*)	targ_emul=elf32l4300 ;;
 mips*vr5000-*-elf*)	targ_emul=elf32b4300 ;;
+mips*allegrexel-psp-elf*) targ_emul=elf_mipsallegrexel_psp
+			targ_extra_emuls="elf32elmip" ;;
 mips*el-*-elf*)		targ_emul=elf32elmip ;;
 mips*-*-elf*)		targ_emul=elf32ebmip ;;
 mips*el-*-rtems*)	targ_emul=elf32elmip ;;
diff -burN binutils-2.16.1/ld/emulparams/elf_mipsallegrexel_psp.sh binutils-psp/ld/emulparams/elf_mipsallegrexel_psp.sh
--- binutils-2.16.1/ld/emulparams/elf_mipsallegrexel_psp.sh	1970-01-01 01:00:00.000000000 +0100
+++ binutils-psp/ld/emulparams/elf_mipsallegrexel_psp.sh	2006-05-09 02:55:36.000000000 +0100
@@ -0,0 +1,22 @@
+# Based off of the default elf32 MIPS target.  However, we use a seperate
+# script template because the PSP architecture defines sections that normally
+# cannot be overriden here and would normally get absorbed (i.e.
+# .rodata.sceModuleInfo would be absorbed into .rodata).
+
+EMBEDDED=yes
+. ${srcdir}/emulparams/elf32lmip.sh
+unset NONPAGED_TEXT_START_ADDR
+unset SHLIB_TEXT_START_ADDR
+unset COMMONPAGESIZE
+
+SCRIPT_NAME=elf_psp
+TEXT_START_ADDR=0x08900000
+MAXPAGESIZE=256
+ARCH="mips:allegrex"
+MACHINE=
+TEMPLATE_NAME=elf32
+GENERATE_SHLIB_SCRIPT=yes
+DYNAMIC_LINK=FALSE
+
+# Discard the .comment and .pdr sections.
+OTHER_SECTIONS="/DISCARD/ : { *(.comment) *(.pdr) }"
diff -burN binutils-2.16.1/ld/Makefile.am binutils-psp/ld/Makefile.am
--- binutils-2.16.1/ld/Makefile.am	2005-01-20 19:37:49.000000000 +0000
+++ binutils-psp/ld/Makefile.am	2006-05-09 02:55:36.000000000 +0100
@@ -190,6 +190,7 @@
 	eelf_i386_chaos.o \
 	eelf_i386_fbsd.o \
 	eelf_i386_ldso.o \
+	eelf_mipsallegrexel_psp.o \
 	eelf_s390.o \
 	egld960.o \
 	egld960coff.o \
@@ -864,6 +865,9 @@
 eelf_i386_ldso.c: $(srcdir)/emulparams/elf_i386_ldso.sh \
   $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} elf_i386_ldso "$(tdir_elf_i386_ldso)"
+eelf_mipsallegrexel_psp.c: $(srcdir)/emulparams/elf_mipsallegrexel_psp.sh \
+  $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf_psp.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} elf_mipsallegrexel_psp "$(tdir_elf_mipsallegrexel_psp)"
 eelf_s390.c: $(srcdir)/emulparams/elf_s390.sh \
   $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} elf_s390 "$(tdir_elf_s390)"
diff -burN binutils-2.16.1/ld/Makefile.in binutils-psp/ld/Makefile.in
--- binutils-2.16.1/ld/Makefile.in	2005-01-23 05:36:37.000000000 +0000
+++ binutils-psp/ld/Makefile.in	2006-05-09 02:55:36.000000000 +0100
@@ -315,6 +315,7 @@
 	eelf_i386_chaos.o \
 	eelf_i386_fbsd.o \
 	eelf_i386_ldso.o \
+	eelf_mipsallegrexel_psp.o \
 	eelf_s390.o \
 	egld960.o \
 	egld960coff.o \
@@ -1601,6 +1602,9 @@
 eelf_i386_ldso.c: $(srcdir)/emulparams/elf_i386_ldso.sh \
   $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} elf_i386_ldso "$(tdir_elf_i386_ldso)"
+eelf_mipsallegrexel_psp.c: $(srcdir)/emulparams/elf_mipsallegrexel_psp.sh \
+  $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf_psp.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} elf_mipsallegrexel_psp "$(tdir_elf_mipsallegrexel_psp)"
 eelf_s390.c: $(srcdir)/emulparams/elf_s390.sh \
   $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} elf_s390 "$(tdir_elf_s390)"
diff -burN binutils-2.16.1/ld/scripttempl/elf_psp.sc binutils-psp/ld/scripttempl/elf_psp.sc
--- binutils-2.16.1/ld/scripttempl/elf_psp.sc	1970-01-01 01:00:00.000000000 +0100
+++ binutils-psp/ld/scripttempl/elf_psp.sc	2006-05-09 02:55:36.000000000 +0100
@@ -0,0 +1,496 @@
+#
+# Unusual variables checked by this code:
+#	NOP - four byte opcode for no-op (defaults to 0)
+#	NO_SMALL_DATA - no .sbss/.sbss2/.sdata/.sdata2 sections if not
+#		empty.
+#	SMALL_DATA_CTOR - .ctors contains small data.
+#	SMALL_DATA_DTOR - .dtors contains small data.
+#	DATA_ADDR - if end-of-text-plus-one-page isn't right for data start
+#	INITIAL_READONLY_SECTIONS - at start of text segment
+#	OTHER_READONLY_SECTIONS - other than .text .init .rodata ...
+#		(e.g., .PARISC.milli)
+#	OTHER_TEXT_SECTIONS - these get put in .text when relocating
+#	OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ...
+#		(e.g., .PARISC.global)
+#	OTHER_RELRO_SECTIONS - other than .data.rel.ro ...
+#		(e.g. PPC32 .fixup, .got[12])
+#	OTHER_BSS_SECTIONS - other than .bss .sbss ...
+#	OTHER_SECTIONS - at the end
+#	EXECUTABLE_SYMBOLS - symbols that must be defined for an
+#		executable (e.g., _DYNAMIC_LINK)
+#       TEXT_START_ADDR - the first byte of the text segment, after any
+#               headers.
+#       TEXT_BASE_ADDRESS - the first byte of the text segment.
+#	TEXT_START_SYMBOLS - symbols that appear at the start of the
+#		.text section.
+#	DATA_START_SYMBOLS - symbols that appear at the start of the
+#		.data section.
+#	OTHER_GOT_SYMBOLS - symbols defined just before .got.
+#	OTHER_GOT_SECTIONS - sections just after .got.
+#	OTHER_SDATA_SECTIONS - sections just after .sdata.
+#	OTHER_BSS_SYMBOLS - symbols that appear at the start of the
+#		.bss section besides __bss_start.
+#	DATA_PLT - .plt should be in data segment, not text segment.
+#	PLT_BEFORE_GOT - .plt just before .got when .plt is in data segement.
+#	BSS_PLT - .plt should be in bss segment
+#	TEXT_DYNAMIC - .dynamic in text segment, not data segment.
+#	EMBEDDED - whether this is for an embedded system. 
+#	SHLIB_TEXT_START_ADDR - if set, add to SIZEOF_HEADERS to set
+#		start address of shared library.
+#	INPUT_FILES - INPUT command of files to always include
+#	WRITABLE_RODATA - if set, the .rodata section should be writable
+#	INIT_START, INIT_END -  statements just before and just after
+# 	combination of .init sections.
+#	FINI_START, FINI_END - statements just before and just after
+# 	combination of .fini sections.
+#	STACK_ADDR - start of a .stack section.
+#	OTHER_END_SYMBOLS - symbols to place right at the end of the script.
+#	SEPARATE_GOTPLT - if set, .got.plt should be separate output section,
+#		so that .got can be in the RELRO area.  It should be set to
+#		the number of bytes in the beginning of .got.plt which can be
+#		in the RELRO area as well.
+#
+# When adding sections, do note that the names of some sections are used
+# when specifying the start address of the next.
+#
+
+#  Many sections come in three flavours.  There is the 'real' section,
+#  like ".data".  Then there are the per-procedure or per-variable
+#  sections, generated by -ffunction-sections and -fdata-sections in GCC,
+#  and useful for --gc-sections, which for a variable "foo" might be
+#  ".data.foo".  Then there are the linkonce sections, for which the linker
+#  eliminates duplicates, which are named like ".gnu.linkonce.d.foo".
+#  The exact correspondences are:
+#
+#  Section	Linkonce section
+#  .text	.gnu.linkonce.t.foo
+#  .rodata	.gnu.linkonce.r.foo
+#  .data	.gnu.linkonce.d.foo
+#  .bss		.gnu.linkonce.b.foo
+#  .sdata	.gnu.linkonce.s.foo
+#  .sbss	.gnu.linkonce.sb.foo
+#  .sdata2	.gnu.linkonce.s2.foo
+#  .sbss2	.gnu.linkonce.sb2.foo
+#  .debug_info	.gnu.linkonce.wi.foo
+#  .tdata	.gnu.linkonce.td.foo
+#  .tbss	.gnu.linkonce.tb.foo
+#
+#  Each of these can also have corresponding .rel.* and .rela.* sections.
+
+test -z "$ENTRY" &amp;&amp; ENTRY=_start
+test -z "${BIG_OUTPUT_FORMAT}" &amp;&amp; BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
+test -z "${LITTLE_OUTPUT_FORMAT}" &amp;&amp; LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
+if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi
+test -z "${ELFSIZE}" &amp;&amp; ELFSIZE=32
+test -z "${ALIGNMENT}" &amp;&amp; ALIGNMENT="${ELFSIZE} / 8"
+test "$LD_FLAG" = "N" &amp;&amp; DATA_ADDR=.
+test -n "$CREATE_SHLIB$CREATE_PIE" &amp;&amp; test -n "$SHLIB_DATA_ADDR" &amp;&amp; COMMONPAGESIZE=""
+test -z "$CREATE_SHLIB$CREATE_PIE" &amp;&amp; test -n "$DATA_ADDR" &amp;&amp; COMMONPAGESIZE=""
+test -n "$RELRO_NOW" &amp;&amp; unset SEPARATE_GOTPLT
+DATA_SEGMENT_ALIGN="ALIGN(${SEGMENT_SIZE}) + (. &amp; (${MAXPAGESIZE} - 1))"
+DATA_SEGMENT_RELRO_END=""
+DATA_SEGMENT_RELRO_GOTPLT_END=""
+DATA_SEGMENT_END=""
+if test -n "${COMMONPAGESIZE}"; then
+  DATA_SEGMENT_ALIGN="ALIGN (${SEGMENT_SIZE}) - ((${MAXPAGESIZE} - .) &amp; (${MAXPAGESIZE} - 1)); . = DATA_SEGMENT_ALIGN (${MAXPAGESIZE}, ${COMMONPAGESIZE})"
+  DATA_SEGMENT_END=". = DATA_SEGMENT_END (.);"
+  if test -n "${SEPARATE_GOTPLT}"; then
+    DATA_SEGMENT_RELRO_GOTPLT_END=". = DATA_SEGMENT_RELRO_END (${SEPARATE_GOTPLT}, .);"
+  else
+    DATA_SEGMENT_RELRO_END=". = DATA_SEGMENT_RELRO_END (0, .);"
+  fi
+fi
+INTERP=".interp       ${RELOCATING-0} : { *(.interp) }"
+PLT=".plt          ${RELOCATING-0} : { *(.plt) }"
+if test -z "$GOT"; then
+  if test -z "$SEPARATE_GOTPLT"; then
+    GOT=".got          ${RELOCATING-0} : { *(.got.plt) *(.got) }"
+  else
+    GOT=".got          ${RELOCATING-0} : { *(.got) }"
+    GOTPLT="${RELOCATING+${DATA_SEGMENT_RELRO_GOTPLT_END}}
+  .got.plt      ${RELOCATING-0} : { *(.got.plt) }"
+  fi
+fi
+DYNAMIC=".dynamic      ${RELOCATING-0} : { *(.dynamic) }"
+RODATA=".rodata       ${RELOCATING-0} : { *(.rodata${RELOCATING+ .rodata.* .gnu.linkonce.r.*}) }"
+DATARELRO=".data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }"
+STACKNOTE="/DISCARD/ : { *(.note.GNU-stack) }"
+if test -z "${NO_SMALL_DATA}"; then
+  SBSS=".sbss         ${RELOCATING-0} :
+  {
+    ${RELOCATING+PROVIDE (__sbss_start = .);}
+    ${RELOCATING+PROVIDE (___sbss_start = .);}
+    ${CREATE_SHLIB+*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)}
+    *(.dynsbss)
+    *(.sbss${RELOCATING+ .sbss.* .gnu.linkonce.sb.*})
+    *(.scommon)
+    ${RELOCATING+PROVIDE (__sbss_end = .);}
+    ${RELOCATING+PROVIDE (___sbss_end = .);}
+  }"
+  SBSS2=".sbss2        ${RELOCATING-0} : { *(.sbss2${RELOCATING+ .sbss2.* .gnu.linkonce.sb2.*}) }"
+  SDATA="/* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata        ${RELOCATING-0} : 
+  {
+    ${RELOCATING+${SDATA_START_SYMBOLS}}
+    ${CREATE_SHLIB+*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)}
+    *(.sdata${RELOCATING+ .sdata.* .gnu.linkonce.s.*})
+  }"
+  SDATA2=".sdata2       ${RELOCATING-0} : { *(.sdata2${RELOCATING+ .sdata2.* .gnu.linkonce.s2.*}) }"
+  REL_SDATA=".rel.sdata    ${RELOCATING-0} : { *(.rel.sdata${RELOCATING+ .rel.sdata.* .rel.gnu.linkonce.s.*}) }
+  .rela.sdata   ${RELOCATING-0} : { *(.rela.sdata${RELOCATING+ .rela.sdata.* .rela.gnu.linkonce.s.*}) }"
+  REL_SBSS=".rel.sbss     ${RELOCATING-0} : { *(.rel.sbss${RELOCATING+ .rel.sbss.* .rel.gnu.linkonce.sb.*}) }
+  .rela.sbss    ${RELOCATING-0} : { *(.rela.sbss${RELOCATING+ .rela.sbss.* .rela.gnu.linkonce.sb.*}) }"
+  REL_SDATA2=".rel.sdata2   ${RELOCATING-0} : { *(.rel.sdata2${RELOCATING+ .rel.sdata2.* .rel.gnu.linkonce.s2.*}) }
+  .rela.sdata2  ${RELOCATING-0} : { *(.rela.sdata2${RELOCATING+ .rela.sdata2.* .rela.gnu.linkonce.s2.*}) }"
+  REL_SBSS2=".rel.sbss2    ${RELOCATING-0} : { *(.rel.sbss2${RELOCATING+ .rel.sbss2.* .rel.gnu.linkonce.sb2.*}) }
+  .rela.sbss2   ${RELOCATING-0} : { *(.rela.sbss2${RELOCATING+ .rela.sbss2.* .rela.gnu.linkonce.sb2.*}) }"
+else
+  NO_SMALL_DATA=" "
+fi
+test -n "$SEPARATE_GOTPLT" &amp;&amp; SEPARATE_GOTPLT=" "
+CTOR=".ctors        ${CONSTRUCTING-0} : 
+  {
+    ${CONSTRUCTING+${CTOR_START}}
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+
+    KEEP (*crtbegin*.o(.ctors))
+
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+
+    KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    ${CONSTRUCTING+${CTOR_END}}
+  }"
+DTOR=".dtors        ${CONSTRUCTING-0} :
+  {
+    ${CONSTRUCTING+${DTOR_START}}
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    ${CONSTRUCTING+${DTOR_END}}
+  }"
+STACK="  .stack        ${RELOCATING-0}${RELOCATING+${STACK_ADDR}} :
+  {
+    ${RELOCATING+_stack = .;}
+    *(.stack)
+  }"
+
+# if this is for an embedded system, don't add SIZEOF_HEADERS.
+if [ -z "$EMBEDDED" ]; then
+   test -z "${TEXT_BASE_ADDRESS}" &amp;&amp; TEXT_BASE_ADDRESS="${TEXT_START_ADDR} + SIZEOF_HEADERS"
+else
+   test -z "${TEXT_BASE_ADDRESS}" &amp;&amp; TEXT_BASE_ADDRESS="${TEXT_START_ADDR}"
+fi
+
+cat &lt;&lt;EOF
+OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
+	      "${LITTLE_OUTPUT_FORMAT}")
+OUTPUT_ARCH(${OUTPUT_ARCH})
+ENTRY(${ENTRY})
+
+${RELOCATING+${LIB_SEARCH_DIRS}}
+${RELOCATING+/* Do we need any of these for elf?
+   __DYNAMIC = 0; ${STACKZERO+${STACKZERO}} ${SHLIB_PATH+${SHLIB_PATH}}  */}
+${RELOCATING+${EXECUTABLE_SYMBOLS}}
+${RELOCATING+${INPUT_FILES}}
+${RELOCATING- /* For some reason, the Solaris linker makes bad executables
+  if gld -r is used and the intermediate file has sections starting
+  at non-zero addresses.  Could be a Solaris ld bug, could be a GNU ld
+  bug.  But for now assigning the zero vmas works.  */}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+PROVIDE (__executable_start = ${TEXT_START_ADDR}); . = ${TEXT_BASE_ADDRESS};}}}
+  ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
+  ${CREATE_PIE+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
+  ${CREATE_SHLIB-${INTERP}}
+  ${INITIAL_READONLY_SECTIONS}
+  ${TEXT_DYNAMIC+${DYNAMIC}}
+  .hash         ${RELOCATING-0} : { *(.hash) }
+  .dynsym       ${RELOCATING-0} : { *(.dynsym) }
+  .dynstr       ${RELOCATING-0} : { *(.dynstr) }
+  .gnu.version  ${RELOCATING-0} : { *(.gnu.version) }
+  .gnu.version_d ${RELOCATING-0}: { *(.gnu.version_d) }
+  .gnu.version_r ${RELOCATING-0}: { *(.gnu.version_r) }
+
+EOF
+if [ "x$COMBRELOC" = x ]; then
+  COMBRELOCCAT=cat
+else
+  COMBRELOCCAT="cat &gt; $COMBRELOC"
+fi
+eval $COMBRELOCCAT &lt;&lt;EOF
+  .rel.init     ${RELOCATING-0} : { *(.rel.init) }
+  .rela.init    ${RELOCATING-0} : { *(.rela.init) }
+  .rel.text     ${RELOCATING-0} : { *(.rel.text${RELOCATING+ .rel.text.* .rel.gnu.linkonce.t.*}) }
+  .rela.text    ${RELOCATING-0} : { *(.rela.text${RELOCATING+ .rela.text.* .rela.gnu.linkonce.t.*}) }
+  .rel.fini     ${RELOCATING-0} : { *(.rel.fini) }
+  .rela.fini    ${RELOCATING-0} : { *(.rela.fini) }
+
+  /* PSP-specific relocations. */
+  .rel.sceStub.text ${RELOCATING-0} : { *(.rel.sceStub.text) *(SORT(.rel.sceStub.text.*)) }
+  .rel.lib.ent.top  ${RELOCATING-0} : { *(.rel.lib.ent.top) }
+  .rel.lib.ent      ${RELOCATING-0} : { *(.rel.lib.ent) }
+  .rel.lib.ent.btm  ${RELOCATING-0} : { *(.rel.lib.ent.btm) }
+  .rel.lib.stub.top ${RELOCATING-0} : { *(.rel.lib.stub.top) }
+  .rel.lib.stub     ${RELOCATING-0} : { *(.rel.lib.stub) }
+  .rel.lib.stub.btm ${RELOCATING-0} : { *(.rel.lib.stub.btm) }
+  .rel.rodata.sceModuleInfo ${RELOCATING-0} : { *(.rel.rodata.sceModuleInfo) }
+  .rel.rodata.sceResident   ${RELOCATING-0} : { *(.rel.rodata.sceResident) }
+  .rel.rodata.sceNid        ${RELOCATING-0} : { *(.rel.rodata.sceNid) }
+  .rel.rodata.sceVstub      ${RELOCATING-0} : { *(.rel.rodata.sceVstub) *(SORT(.rel.rodata.sceVstub.*)) }
+
+  .rel.rodata   ${RELOCATING-0} : { *(.rel.rodata${RELOCATING+ .rel.rodata.* .rel.gnu.linkonce.r.*}) }
+  .rela.rodata  ${RELOCATING-0} : { *(.rela.rodata${RELOCATING+ .rela.rodata.* .rela.gnu.linkonce.r.*}) }
+  ${OTHER_READONLY_RELOC_SECTIONS}
+  .rel.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }
+  .rela.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }
+  .rel.data     ${RELOCATING-0} : { *(.rel.data${RELOCATING+ .rel.data.* .rel.gnu.linkonce.d.*}) }
+  .rela.data    ${RELOCATING-0} : { *(.rela.data${RELOCATING+ .rela.data.* .rela.gnu.linkonce.d.*}) }
+  .rel.tdata	${RELOCATING-0} : { *(.rel.tdata${RELOCATING+ .rel.tdata.* .rel.gnu.linkonce.td.*}) }
+  .rela.tdata	${RELOCATING-0} : { *(.rela.tdata${RELOCATING+ .rela.tdata.* .rela.gnu.linkonce.td.*}) }
+  .rel.tbss	${RELOCATING-0} : { *(.rel.tbss${RELOCATING+ .rel.tbss.* .rel.gnu.linkonce.tb.*}) }
+  .rela.tbss	${RELOCATING-0} : { *(.rela.tbss${RELOCATING+ .rela.tbss.* .rela.gnu.linkonce.tb.*}) }
+  .rel.ctors    ${RELOCATING-0} : { *(.rel.ctors) }
+  .rela.ctors   ${RELOCATING-0} : { *(.rela.ctors) }
+  .rel.dtors    ${RELOCATING-0} : { *(.rel.dtors) }
+  .rela.dtors   ${RELOCATING-0} : { *(.rela.dtors) }
+  .rel.got      ${RELOCATING-0} : { *(.rel.got) }
+  .rela.got     ${RELOCATING-0} : { *(.rela.got) }
+  ${OTHER_GOT_RELOC_SECTIONS}
+  ${REL_SDATA}
+  ${REL_SBSS}
+  ${REL_SDATA2}
+  ${REL_SBSS2}
+  .rel.bss      ${RELOCATING-0} : { *(.rel.bss${RELOCATING+ .rel.bss.* .rel.gnu.linkonce.b.*}) }
+  .rela.bss     ${RELOCATING-0} : { *(.rela.bss${RELOCATING+ .rela.bss.* .rela.gnu.linkonce.b.*}) }
+EOF
+if [ -n "$COMBRELOC" ]; then
+cat &lt;&lt;EOF
+  .rel.dyn      ${RELOCATING-0} :
+    {
+EOF
+sed -e '/^[ 	]*[{}][ 	]*$/d;/:[ 	]*$/d;/\.rela\./d;s/^.*: { *\(.*\)}$/      \1/' $COMBRELOC
+cat &lt;&lt;EOF
+    }
+  .rela.dyn     ${RELOCATING-0} :
+    {
+EOF
+sed -e '/^[ 	]*[{}][ 	]*$/d;/:[ 	]*$/d;/\.rel\./d;s/^.*: { *\(.*\)}/      \1/' $COMBRELOC
+cat &lt;&lt;EOF
+    }
+EOF
+fi
+cat &lt;&lt;EOF
+  .rel.plt      ${RELOCATING-0} : { *(.rel.plt) }
+  .rela.plt     ${RELOCATING-0} : { *(.rela.plt) }
+  ${OTHER_PLT_RELOC_SECTIONS}
+
+  .init         ${RELOCATING-0} : 
+  { 
+    ${RELOCATING+${INIT_START}}
+    KEEP (*(.init))
+    ${RELOCATING+${INIT_END}}
+  } =${NOP-0}
+
+  ${DATA_PLT-${BSS_PLT-${PLT}}}
+  .text         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${TEXT_START_SYMBOLS}}
+    *(.text .stub${RELOCATING+ .text.* .gnu.linkonce.t.*})
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    ${RELOCATING+${OTHER_TEXT_SECTIONS}}
+  } =${NOP-0}
+  .fini         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${FINI_START}}
+    KEEP (*(.fini))
+    ${RELOCATING+${FINI_END}}
+  } =${NOP-0}
+
+  /* PSP library stub functions. */
+  .sceStub.text   ${RELOCATING-0} : { *(.sceStub.text) *(SORT(.sceStub.text.*)) }
+
+  ${RELOCATING+PROVIDE (__etext = .);}
+  ${RELOCATING+PROVIDE (_etext = .);}
+  ${RELOCATING+PROVIDE (etext = .);}
+
+  /* PSP library entry table and library stub table. */
+  .lib.ent.top  ${RELOCATING-0} : { *(.lib.ent.top) }
+  .lib.ent      ${RELOCATING-0} : { *(.lib.ent) }
+  .lib.ent.btm  ${RELOCATING-0} : { *(.lib.ent.btm) }
+
+  .lib.stub.top ${RELOCATING-0} : { *(.lib.stub.top) }
+  .lib.stub     ${RELOCATING-0} : { *(.lib.stub) }
+  .lib.stub.btm ${RELOCATING-0} : { *(.lib.stub.btm) }
+
+  /* PSP read-only data for module info, NIDs, and Vstubs.  The
+     .rodata.sceModuleInfo section must appear before the .rodata section
+     otherwise it would get absorbed into .rodata and the PSP bootloader
+     would be unable to locate the module info structure. */
+  .rodata.sceModuleInfo  ${RELOCATING-0} : { *(.rodata.sceModuleInfo) }
+  .rodata.sceResident    ${RELOCATING-0} : { *(.rodata.sceResident) }
+  .rodata.sceNid         ${RELOCATING-0} : { *(.rodata.sceNid) }
+  .rodata.sceVstub       ${RELOCATING-0} : { *(.rodata.sceVstub) *(SORT(.rodata.sceVstub.*)) }
+
+  ${WRITABLE_RODATA-${RODATA}}
+  .rodata1      ${RELOCATING-0} : { *(.rodata1) }
+  ${CREATE_SHLIB-${SDATA2}}
+  ${CREATE_SHLIB-${SBSS2}}
+  ${OTHER_READONLY_SECTIONS}
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+  .eh_frame     ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+  .gcc_except_table ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
+
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+. = ${DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}}
+  ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}
+  ${CREATE_PIE+${RELOCATING+. = ${SHLIB_DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}
+
+  /* Exception handling  */
+  .eh_frame     ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.eh_frame)) }
+  .gcc_except_table ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
+
+  /* Thread Local Storage sections  */
+  .tdata	${RELOCATING-0} : { *(.tdata${RELOCATING+ .tdata.* .gnu.linkonce.td.*}) }
+  .tbss		${RELOCATING-0} : { *(.tbss${RELOCATING+ .tbss.* .gnu.linkonce.tb.*})${RELOCATING+ *(.tcommon)} }
+
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  ${RELOCATING+. = ALIGN(${ALIGNMENT});}
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_start = .);}}
+  .preinit_array   ${RELOCATING-0} : { KEEP (*(.preinit_array)) }
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_end = .);}}
+
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_start = .);}}
+  .init_array   ${RELOCATING-0} : { KEEP (*(.init_array)) }
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_end = .);}}
+
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_start = .);}}
+  .fini_array   ${RELOCATING-0} : { KEEP (*(.fini_array)) }
+  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_end = .);}}
+
+  ${SMALL_DATA_CTOR-${RELOCATING+${CTOR}}}
+  ${SMALL_DATA_DTOR-${RELOCATING+${DTOR}}}
+  .jcr          ${RELOCATING-0} : { KEEP (*(.jcr)) }
+
+  ${RELOCATING+${DATARELRO}}
+  ${OTHER_RELRO_SECTIONS}
+  ${TEXT_DYNAMIC-${DYNAMIC}}
+  ${NO_SMALL_DATA+${RELRO_NOW+${GOT}}}
+  ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOT}}}}
+  ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOTPLT}}}}
+  ${RELOCATING+${DATA_SEGMENT_RELRO_END}}
+  ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT-${GOT}}}}
+
+  ${DATA_PLT+${PLT_BEFORE_GOT-${PLT}}}
+
+  .data         ${RELOCATING-0} :
+  {
+    ${RELOCATING+${DATA_START_SYMBOLS}}
+    *(.data${RELOCATING+ .data.* .gnu.linkonce.d.*})
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    ${CONSTRUCTING+SORT(CONSTRUCTORS)}
+  }
+  .data1        ${RELOCATING-0} : { *(.data1) }
+  ${WRITABLE_RODATA+${RODATA}}
+  ${OTHER_READWRITE_SECTIONS}
+  ${SMALL_DATA_CTOR+${RELOCATING+${CTOR}}}
+  ${SMALL_DATA_DTOR+${RELOCATING+${DTOR}}}
+  ${DATA_PLT+${PLT_BEFORE_GOT+${PLT}}}
+  ${RELOCATING+${OTHER_GOT_SYMBOLS}}
+  ${NO_SMALL_DATA-${GOT}}
+  ${OTHER_GOT_SECTIONS}
+  ${SDATA}
+  ${OTHER_SDATA_SECTIONS}
+  ${RELOCATING+_edata = .;}
+  ${RELOCATING+PROVIDE (edata = .);}
+  ${RELOCATING+__bss_start = .;}
+  ${RELOCATING+${OTHER_BSS_SYMBOLS}}
+  ${SBSS}
+  ${BSS_PLT+${PLT}}
+  .bss          ${RELOCATING-0} :
+  {
+   *(.dynbss)
+   *(.bss${RELOCATING+ .bss.* .gnu.linkonce.b.*})
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   ${RELOCATING+. = ALIGN(${ALIGNMENT});}
+  }
+  ${OTHER_BSS_SECTIONS}
+  ${RELOCATING+. = ALIGN(${ALIGNMENT});}
+  ${RELOCATING+_end = .;}
+  ${RELOCATING+${OTHER_BSS_END_SYMBOLS}}
+  ${RELOCATING+PROVIDE (end = .);}
+  ${RELOCATING+${DATA_SEGMENT_END}}
+
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+
+  .comment       0 : { *(.comment) }
+
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+  ${STACK_ADDR+${STACK}}
+  ${OTHER_SECTIONS}
+  ${RELOCATING+${OTHER_END_SYMBOLS}}
+  ${RELOCATING+${STACKNOTE}}
+}
+EOF
diff -burN binutils-2.16.1/opcodes/mips-dis.c binutils-psp/opcodes/mips-dis.c
--- binutils-2.16.1/opcodes/mips-dis.c	2005-03-03 11:49:50.000000000 +0000
+++ binutils-psp/opcodes/mips-dis.c	2006-05-09 02:55:36.000000000 +0100
@@ -140,6 +140,139 @@
   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
 };
 
+static const char * const vfpu_sreg_names[128] = {
+  "S000",  "S010",  "S020",  "S030",  "S100",  "S110",  "S120",  "S130",
+  "S200",  "S210",  "S220",  "S230",  "S300",  "S310",  "S320",  "S330",
+  "S400",  "S410",  "S420",  "S430",  "S500",  "S510",  "S520",  "S530",
+  "S600",  "S610",  "S620",  "S630",  "S700",  "S710",  "S720",  "S730",
+  "S001",  "S011",  "S021",  "S031",  "S101",  "S111",  "S121",  "S131",
+  "S201",  "S211",  "S221",  "S231",  "S301",  "S311",  "S321",  "S331",
+  "S401",  "S411",  "S421",  "S431",  "S501",  "S511",  "S521",  "S531",
+  "S601",  "S611",  "S621",  "S631",  "S701",  "S711",  "S721",  "S731",
+  "S002",  "S012",  "S022",  "S032",  "S102",  "S112",  "S122",  "S132",
+  "S202",  "S212",  "S222",  "S232",  "S302",  "S312",  "S322",  "S332",
+  "S402",  "S412",  "S422",  "S432",  "S502",  "S512",  "S522",  "S532",
+  "S602",  "S612",  "S622",  "S632",  "S702",  "S712",  "S722",  "S732",
+  "S003",  "S013",  "S023",  "S033",  "S103",  "S113",  "S123",  "S133",
+  "S203",  "S213",  "S223",  "S233",  "S303",  "S313",  "S323",  "S333",
+  "S403",  "S413",  "S423",  "S433",  "S503",  "S513",  "S523",  "S533",
+  "S603",  "S613",  "S623",  "S633",  "S703",  "S713",  "S723",  "S733"
+};
+
+static const char * const vfpu_vpreg_names[128] = {
+  "C000",  "C010",  "C020",  "C030",  "C100",  "C110",  "C120",  "C130",
+  "C200",  "C210",  "C220",  "C230",  "C300",  "C310",  "C320",  "C330",
+  "C400",  "C410",  "C420",  "C430",  "C500",  "C510",  "C520",  "C530",
+  "C600",  "C610",  "C620",  "C630",  "C700",  "C710",  "C720",  "C730",
+  "R000",  "R001",  "R002",  "R003",  "R100",  "R101",  "R102",  "R103",
+  "R200",  "R201",  "R202",  "R203",  "R300",  "R301",  "R302",  "R303",
+  "R400",  "R401",  "R402",  "R403",  "R500",  "R501",  "R502",  "R503",
+  "R600",  "R601",  "R602",  "R603",  "R700",  "R701",  "R702",  "R703",
+  "C002",  "C012",  "C022",  "C032",  "C102",  "C112",  "C122",  "C132",
+  "C202",  "C212",  "C222",  "C232",  "C302",  "C312",  "C322",  "C332",
+  "C402",  "C412",  "C422",  "C432",  "C502",  "C512",  "C522",  "C532",
+  "C602",  "C612",  "C622",  "C632",  "C702",  "C712",  "C722",  "C732",
+  "R020",  "R021",  "R022",  "R023",  "R120",  "R121",  "R122",  "R123",
+  "R220",  "R221",  "R222",  "R223",  "R320",  "R321",  "R322",  "R323",
+  "R420",  "R421",  "R422",  "R423",  "R520",  "R521",  "R522",  "R523",
+  "R620",  "R621",  "R622",  "R623",  "R720",  "R721",  "R722",  "R723"
+};
+
+static const char * const vfpu_vtreg_names[128] = {
+  "C000",  "C010",  "C020",  "C030",  "C100",  "C110",  "C120",  "C130",
+  "C200",  "C210",  "C220",  "C230",  "C300",  "C310",  "C320",  "C330",
+  "C400",  "C410",  "C420",  "C430",  "C500",  "C510",  "C520",  "C530",
+  "C600",  "C610",  "C620",  "C630",  "C700",  "C710",  "C720",  "C730",
+  "R000",  "R001",  "R002",  "R003",  "R100",  "R101",  "R102",  "R103",
+  "R200",  "R201",  "R202",  "R203",  "R300",  "R301",  "R302",  "R303",
+  "R400",  "R401",  "R402",  "R403",  "R500",  "R501",  "R502",  "R503",
+  "R600",  "R601",  "R602",  "R603",  "R700",  "R701",  "R702",  "R703",
+  "C001",  "C011",  "C021",  "C031",  "C101",  "C111",  "C121",  "C131",
+  "C201",  "C211",  "C221",  "C231",  "C301",  "C311",  "C321",  "C331",
+  "C401",  "C411",  "C421",  "C431",  "C501",  "C511",  "C521",  "C531",
+  "C601",  "C611",  "C621",  "C631",  "C701",  "C711",  "C721",  "C731",
+  "R010",  "R011",  "R012",  "R013",  "R110",  "R111",  "R112",  "R113",
+  "R210",  "R211",  "R212",  "R213",  "R310",  "R311",  "R312",  "R313",
+  "R410",  "R411",  "R412",  "R413",  "R510",  "R511",  "R512",  "R513",
+  "R610",  "R611",  "R612",  "R613",  "R710",  "R711",  "R712",  "R713"
+};
+
+static const char * const vfpu_vqreg_names[128] = {
+  "C000",  "C010",  "C020",  "C030",  "C100",  "C110",  "C120",  "C130",
+  "C200",  "C210",  "C220",  "C230",  "C300",  "C310",  "C320",  "C330",
+  "C400",  "C410",  "C420",  "C430",  "C500",  "C510",  "C520",  "C530",
+  "C600",  "C610",  "C620",  "C630",  "C700",  "C710",  "C720",  "C730",
+  "R000",  "R001",  "R002",  "R003",  "R100",  "R101",  "R102",  "R103",
+  "R200",  "R201",  "R202",  "R203",  "R300",  "R301",  "R302",  "R303",
+  "R400",  "R401",  "R402",  "R403",  "R500",  "R501",  "R502",  "R503",
+  "R600",  "R601",  "R602",  "R603",  "R700",  "R701",  "R702",  "R703",
+  "",  "",  "",  "",  "",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  ""
+};
+
+static const char * const vfpu_mpreg_names[128] = {
+  "M000",  "",  "M020",  "",  "M100",  "",  "M120",  "",
+  "M200",  "",  "M220",  "",  "M300",  "",  "M320",  "",
+  "M400",  "",  "M420",  "",  "M500",  "",  "M520",  "",
+  "M600",  "",  "M620",  "",  "M700",  "",  "M720",  "",
+  "E000",  "",  "E002",  "",  "E100",  "",  "E102",  "",
+  "E200",  "",  "E202",  "",  "E300",  "",  "E302",  "",
+  "E400",  "",  "E402",  "",  "E500",  "",  "E502",  "",
+  "E600",  "",  "E602",  "",  "E700",  "",  "E702",  "",
+  "M002",  "",  "M022",  "",  "M102",  "",  "M122",  "",
+  "M202",  "",  "M222",  "",  "M302",  "",  "M322",  "",
+  "M402",  "",  "M422",  "",  "M502",  "",  "M522",  "",
+  "M602",  "",  "M622",  "",  "M702",  "",  "M722",  "",
+  "E020",  "",  "E022",  "",  "E120",  "",  "E122",  "",
+  "E220",  "",  "E222",  "",  "E320",  "",  "E322",  "",
+  "E420",  "",  "E422",  "",  "E520",  "",  "E522",  "",
+  "E620",  "",  "E622",  "",  "E720",  "",  "E722",  ""
+};
+
+static const char * const vfpu_mtreg_names[128] = {
+  "M000",  "M010",  "",  "",  "M100",  "M110",  "",  "",
+  "M200",  "M210",  "",  "",  "M300",  "M310",  "",  "",
+  "M400",  "M410",  "",  "",  "M500",  "M510",  "",  "",
+  "M600",  "M610",  "",  "",  "M700",  "M710",  "",  "",
+  "E000",  "E001",  "",  "",  "E100",  "E101",  "",  "",
+  "E200",  "E201",  "",  "",  "E300",  "E301",  "",  "",
+  "E400",  "E401",  "",  "",  "E500",  "E501",  "",  "",
+  "E600",  "E601",  "",  "",  "E700",  "E701",  "",  "",
+  "M001",  "M011",  "",  "",  "M101",  "M111",  "",  "",
+  "M201",  "M211",  "",  "",  "M301",  "M311",  "",  "",
+  "M401",  "M411",  "",  "",  "M501",  "M511",  "",  "",
+  "M601",  "M611",  "",  "",  "M701",  "M711",  "",  "",
+  "E010",  "E011",  "",  "",  "E110",  "E111",  "",  "",
+  "E210",  "E211",  "",  "",  "E310",  "E311",  "",  "",
+  "E410",  "E411",  "",  "",  "E510",  "E511",  "",  "",
+  "E610",  "E611",  "",  "",  "E710",  "E711",  "",  ""
+};
+
+static const char * const vfpu_mqreg_names[128] = {
+  "M000",  "",  "",  "",  "M100",  "",  "",  "",
+  "M200",  "",  "",  "",  "M300",  "",  "",  "",
+  "M400",  "",  "",  "",  "M500",  "",  "",  "",
+  "M600",  "",  "",  "",  "M700",  "",  "",  "",
+  "E000",  "",  "",  "",  "E100",  "",  "",  "",
+  "E200",  "",  "",  "",  "E300",  "",  "",  "",
+  "E400",  "",  "",  "",  "E500",  "",  "",  "",
+  "E600",  "",  "",  "",  "E700",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  "",
+  "",  "",  "",  "",  "",  "",  "",  ""
+};
+
 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = {
   { 16, 1, "c0_config1"		},
   { 16, 2, "c0_config2"		},
@@ -288,6 +421,54 @@
   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
 };
 
+static const char * const vfpu_cond_names[16] = {
+  "FL",  "EQ",  "LT",  "LE",  "TR",  "NE",  "GE",  "GT",
+  "EZ",  "EN",  "EI",  "ES",  "NZ",  "NN",  "NI",  "NS"
+};
+
+static const char * const vfpu_const_names[20] = {
+  "",
+  "VFPU_HUGE",
+  "VFPU_SQRT2",
+  "VFPU_SQRT1_2",
+  "VFPU_2_SQRTPI",
+  "VFPU_2_PI",
+  "VFPU_1_PI",
+  "VFPU_PI_4",
+  "VFPU_PI_2",
+  "VFPU_PI",
+  "VFPU_E",
+  "VFPU_LOG2E",
+  "VFPU_LOG10E",
+  "VFPU_LN2",
+  "VFPU_LN10",
+  "VFPU_2PI",
+  "VFPU_PI_6",
+  "VFPU_LOG10TWO",
+  "VFPU_LOG2TEN",
+  "VFPU_SQRT3_2"
+};
+
+#define VFPU_NUM_CONSTANTS \
+  ((sizeof vfpu_const_names) / (sizeof (vfpu_const_names[0])))
+const unsigned int vfpu_num_constants = VFPU_NUM_CONSTANTS;
+
+static const char * const vfpu_rwb_names[4] = {
+  "wt",  "wb",  "",  ""
+};
+
+static const char * const pfx_cst_names[8] = {
+  "0",  "1",  "2",  "1/2",  "3",  "1/3",  "1/4",  "1/6"
+};
+
+static const char * const pfx_swz_names[4] = {
+  "x",  "y",  "z",  "w"
+};
+
+static const char * const pfx_sat_names[4] = {
+  "",  "[0:1]",  "",  "[-1:1]"
+};
+
 struct mips_abi_choice {
   const char *name;
   const char * const *gpr_names;
@@ -359,6 +540,8 @@
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "mips5",	1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+  { "allegrex", 1, bfd_mach_mips_allegrex, CPU_ALLEGREX, ISA_MIPS2,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
 
   /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
      Note that MIPS-3D and MDMX are not applicable to MIPS32.  (See
@@ -1031,6 +1214,349 @@
 				 (l &gt;&gt; OP_SH_FT) &amp; OP_MASK_FT);
 	  break;
 
+	case '?':
+	  /* VFPU extensions.  */
+	  d++;
+	  switch (*d)
+	    {
+	    case '\0':
+	      /* xgettext:c-format */
+	      (*info-&gt;fprintf_func) (info-&gt;stream,
+				     _("# internal error, incomplete VFPU extension sequence (?)"));
+	      return;
+
+	    case 'o':
+	      delta = (l &gt;&gt; OP_SH_VFPU_DELTA) &amp; OP_MASK_VFPU_DELTA;
+	      if (delta &amp; 0x8000)
+		delta |= ~0xffff;
+	      (*info-&gt;fprintf_func) (info-&gt;stream, "%d",
+				     delta);
+	      break;
+
+	    case '0':
+	    case '1':
+	    case '2':
+	    case '3':
+	      {
+		unsigned int pos = *d, base = '0';
+		unsigned int negation = (l &gt;&gt; (pos - (base - VFPU_SH_PFX_NEG))) &amp; VFPU_MASK_PFX_NEG;
+		unsigned int constant = (l &gt;&gt; (pos - (base - VFPU_SH_PFX_CST))) &amp; VFPU_MASK_PFX_CST;
+		unsigned int abs_consthi =
+		    (l &gt;&gt; (pos - (base - VFPU_SH_PFX_ABS_CSTHI))) &amp; VFPU_MASK_PFX_ABS_CSTHI;
+		unsigned int swz_constlo = (l &gt;&gt; ((pos - base) * 2)) &amp; VFPU_MASK_PFX_SWZ_CSTLO;
+
+		if (negation)
+		  (*info-&gt;fprintf_func) (info-&gt;stream, "-");
+		if (constant)
+		  {
+		    (*info-&gt;fprintf_func) (info-&gt;stream, "%s",
+                                           pfx_cst_names[(abs_consthi &lt;&lt; 2) | swz_constlo]);
+		  }
+		else
+		  {
+		    if (abs_consthi)
+		      (*info-&gt;fprintf_func) (info-&gt;stream, "|%s|",
+					     pfx_swz_names[swz_constlo]);
+		    else
+		      (*info-&gt;fprintf_func) (info-&gt;stream, "%s",
+					     pfx_swz_names[swz_constlo]);
+		  }
+	      }
+	      break;
+
+	    case '4':
+	    case '5':
+	    case '6':
+	    case '7':
+	      {
+		unsigned int pos = *d, base = '4';
+		unsigned int mask = (l &gt;&gt; (pos - (base - VFPU_SH_PFX_MASK))) &amp; VFPU_MASK_PFX_MASK;
+		unsigned int saturation = (l &gt;&gt; ((pos - base) * 2)) &amp; VFPU_MASK_PFX_SAT;
+
+		if (mask)
+		  (*info-&gt;fprintf_func) (info-&gt;stream, "m");
+		else
+		  (*info-&gt;fprintf_func) (info-&gt;stream, "%s",
+                                         pfx_sat_names[saturation]);
+	      }
+	      break;
+
+	    case 'a':
+	      {
+		unsigned int c = (l &gt;&gt; OP_SH_VFPU_CONST) &amp; OP_MASK_VFPU_CONST;
+		if (c &lt; vfpu_num_constants)
+		  {
+		    (*info-&gt;fprintf_func) (info-&gt;stream, "%s",
+					   vfpu_const_names[c]);
+		  }
+		break;
+	      }
+
+	    case 'b':
+	      /* 5-bit immediate value.  */
+	      (*info-&gt;fprintf_func) (info-&gt;stream, "%d",
+				     (l &gt;&gt; OP_SH_VFPU_IMM5) &amp; OP_MASK_VFPU_IMM5);
+	      break;
+
+	    case 'c':
+	      /* VFPU condition code.  */
+	      (*info-&gt;fprintf_func) (info-&gt;stream, "%d",
+				     (l &gt;&gt; OP_SH_VFPU_CC) &amp; OP_MASK_VFPU_CC);
+	      break;
+
+	    case 'e':
+	      /* 3-bit immediate value.  */
+	      (*info-&gt;fprintf_func) (info-&gt;stream, "%d",
+				     (l &gt;&gt; OP_SH_VFPU_IMM3) &amp; OP_MASK_VFPU_IMM3);
+	      break;
+
+	    case 'f':
+	      /* Conditional compare.  */
+	      (*info-&gt;fprintf_func) (info-&gt;stream, "%s",
+				     vfpu_cond_names[(l &gt;&gt; OP_SH_VFPU_COND) &amp; OP_MASK_VFPU_COND]);
+	      /* Apparently this specifier is unused.  */
+	      d++;
+	      break;
+
+	    case 'i':
+	      /* 8-bit immediate value.  */
+	      (*info-&gt;fprintf_func) (info-&gt;stream, "0x%02x",
+				     (l &gt;&gt; OP_SH_VFPU_IMM8) &amp; OP_MASK_VFPU_IMM8);
+	      break;
+
+	    case 'q':
+	      /* VFPU control register (vmtvc).  */
+	      (*info-&gt;fprintf_func) (info-&gt;stream, "$%d",
+				     (l &gt;&gt; OP_SH_VFPU_VMTVC) &amp; OP_MASK_VFPU_VMTVC);
+	      break;
+
+	    case 'r':
+	      /* VFPU control register (vmfvc).  */
+	      (*info-&gt;fprintf_func) (info-&gt;stream, "$%d",
+				     (l &gt;&gt; OP_SH_VFPU_VMFVC) &amp; OP_MASK_VFPU_VMFVC);
+	      break;
+
+	    case 'u':
+	      /* Convert a VFPU 16-bit floating-point number to IEEE754. */
+	      {
+		union float2int {
+			unsigned int i;
+			float f;
+		} float2int;
+		unsigned short float16 = (l &gt;&gt; OP_SH_VFPU_FLOAT16) &amp; OP_MASK_VFPU_FLOAT16;
+		unsigned int sign = (float16 &gt;&gt; VFPU_SH_FLOAT16_SIGN) &amp; VFPU_MASK_FLOAT16_SIGN;
+		int exponent = (float16 &gt;&gt; VFPU_SH_FLOAT16_EXP) &amp; VFPU_MASK_FLOAT16_EXP;
+		unsigned int fraction = float16 &amp; VFPU_MASK_FLOAT16_FRAC;
+		char signchar = '+' + ((sign == 1) * 2);
+
+		if (exponent == VFPU_FLOAT16_EXP_MAX)
+		  {
+		    if (fraction == 0)
+		      (*info-&gt;fprintf_func) (info-&gt;stream, "%cInf", signchar);
+		    else
+		      (*info-&gt;fprintf_func) (info-&gt;stream, "%cNaN", signchar);
+		  }
+		else if (exponent == 0 &amp;&amp; fraction == 0)
+		  {
+		    (*info-&gt;fprintf_func) (info-&gt;stream, "%c0", signchar);
+		  }
+		else
+		  {
+		    if (exponent == 0)
+		      {
+			do
+			  {
+			    fraction &lt;&lt;= 1;
+			    exponent--;
+			  }
+			while (!(fraction &amp; (VFPU_MASK_FLOAT16_FRAC + 1)));
+
+			fraction &amp;= VFPU_MASK_FLOAT16_FRAC;
+		      }
+
+		    /* Convert to 32-bit single-precision IEEE754. */
+		    float2int.i = sign &lt;&lt; 31;
+		    float2int.i |= (exponent + 112) &lt;&lt; 23;
+		    float2int.i |= fraction &lt;&lt; 13;
+		    (*info-&gt;fprintf_func) (info-&gt;stream, "%g", float2int.f);
+		  }
+	      }
+	      break;
+
+	    case 'w':
+	      {
+		const char *elements[4];
+		unsigned int opcode = l &amp; VFPU_MASK_OP_SIZE;
+		unsigned int rotators = (l &gt;&gt; OP_SH_VFPU_ROT) &amp; OP_MASK_VFPU_ROT;
+		unsigned int opsize, rothi, rotlo, negation, i;
+
+		/* Determine the operand size so we'll know how many elements to output. */
+		if (opcode == VFPU_OP_SIZE_PAIR)
+		  opsize = 2;
+		else if (opcode == VFPU_OP_SIZE_TRIPLE)
+		  opsize = 3;
+		else
+		  opsize = (opcode == VFPU_OP_SIZE_QUAD) * 4;	/* Sanity check. */
+
+		rothi = (rotators &gt;&gt; VFPU_SH_ROT_HI) &amp; VFPU_MASK_ROT_HI;
+		rotlo = (rotators &gt;&gt; VFPU_SH_ROT_LO) &amp; VFPU_MASK_ROT_LO;
+		negation = (rotators &gt;&gt; VFPU_SH_ROT_NEG) &amp; VFPU_MASK_ROT_NEG;
+
+		if (rothi == rotlo)
+		  {
+		    if (negation)
+		      {
+			elements[0] = "-s";
+			elements[1] = "-s";
+			elements[2] = "-s";
+			elements[3] = "-s";
+		      }
+		    else
+		      {
+			elements[0] = "s";
+			elements[1] = "s";
+			elements[2] = "s";
+			elements[3] = "s";
+		      }
+		  }
+		else
+		  {
+		    elements[0] = "0";
+		    elements[1] = "0";
+		    elements[2] = "0";
+		    elements[3] = "0";
+		  }
+		if (negation)
+		  elements[rothi] = "-s";
+		else
+		  elements[rothi] = "s";
+		elements[rotlo] = "c";
+
+		(*info-&gt;fprintf_func) (info-&gt;stream, "[");
+		i = 0;
+		for (;;)
+		  {
+		    (*info-&gt;fprintf_func) (info-&gt;stream, "%s",
+					   elements[i++]);
+		    if (i &gt;= opsize)
+		      break;
+		    (*info-&gt;fprintf_func) (info-&gt;stream, ",");
+		  }
+		(*info-&gt;fprintf_func) (info-&gt;stream, "]");
+	      }
+	      break;
+
+	    case 'd':
+	    case 'm':
+	    case 'n':
+	    case 's':
+	    case 't':
+	    case 'v':
+	    case 'x':
+	      {
+		unsigned int vreg = 0;
+
+		/* The first char specifies the bitfield that contains the register number. */
+		switch (*d)
+		  {
+		  case 'd':
+		  case 'v':
+		  case 'x':
+		    vreg = (l &gt;&gt; OP_SH_VFPU_VD) &amp; OP_MASK_VFPU_VD;
+		    break;
+
+		  case 'm':
+		    /* Combine bits 0-4 of vt with bits 5-6 of vt. */
+		    vreg = ((l &gt;&gt; OP_SH_VFPU_VT_LO) &amp; OP_MASK_VFPU_VT_LO)
+			    | ((l &amp; OP_MASK_VFPU_VT_HI2) &lt;&lt; OP_SH_VFPU_VT_HI);
+		    break;
+
+		  case 'n':
+		    /* Combine bits 0-4 of vt with bit 5 of vt. */
+		    vreg = ((l &gt;&gt; OP_SH_VFPU_VT_LO) &amp; OP_MASK_VFPU_VT_LO)
+			    | ((l &amp; OP_MASK_VFPU_VT_HI1) &lt;&lt; OP_SH_VFPU_VT_HI);
+		    break;
+
+		  case 's':
+		    {
+			unsigned int temp_vreg = l &gt;&gt; OP_SH_VFPU_VS;
+
+			vreg = temp_vreg &amp; OP_MASK_VFPU_VS;
+			if ((l &amp; VFPU_OP_VT_VS_VD) == VFPU_OPCODE_VMMUL)
+			  {
+			    /* vmmul instructions have the RXC bit (bit 13) inverted. */
+			    if (temp_vreg &amp; 0x20)
+			      vreg = temp_vreg &amp; 0x5f;
+			    else
+			      vreg |= 0x20;
+			  }
+		    }
+		    break;
+
+		  case 't':
+		    vreg = (l &gt;&gt; OP_SH_VFPU_VT) &amp; OP_MASK_VFPU_VT;
+		    break;
+		  }
+
+		/* The next char is the register set vreg comes from. */
+		d++;
+		switch (*d)
+		  {
+		  case '0':
+		    (*info-&gt;fprintf_func) (info-&gt;stream, "%s.s",
+					   vfpu_sreg_names[vreg]);
+		    break;
+
+		  case '1':
+		    (*info-&gt;fprintf_func) (info-&gt;stream, "%s.p",
+					   vfpu_vpreg_names[vreg]);
+		    break;
+
+		  case '2':
+		    (*info-&gt;fprintf_func) (info-&gt;stream, "%s.t",
+					   vfpu_vtreg_names[vreg]);
+		    break;
+
+		  case '3':
+		    (*info-&gt;fprintf_func) (info-&gt;stream, "%s.q",
+					   vfpu_vqreg_names[vreg]);
+		    break;
+
+		  case '5':
+		    (*info-&gt;fprintf_func) (info-&gt;stream, "%s.p",
+					   vfpu_mpreg_names[vreg]);
+		    break;
+
+		  case '6':
+		    (*info-&gt;fprintf_func) (info-&gt;stream, "%s.t",
+					   vfpu_mtreg_names[vreg]);
+		    break;
+
+		  case '7':
+		    (*info-&gt;fprintf_func) (info-&gt;stream, "%s.q",
+					   vfpu_mqreg_names[vreg]);
+		    break;
+
+		  default:
+		    /* xgettext:c-format */
+		    (*info-&gt;fprintf_func) (info-&gt;stream,
+					   _("# internal error, undefined vreg modifier(%c)"),
+					   *d);
+		    break;
+		  }
+
+		/* The last char is unused for disassembly. */
+		d++;
+	      }
+	      break;
+
+	    case 'z':
+	      (*info-&gt;fprintf_func) (info-&gt;stream, "%s",
+				     vfpu_rwb_names[(l &gt;&gt; OP_SH_VFPU_RWB) &amp; OP_MASK_VFPU_RWB]);
+	      break;
+	    }
+	  break;
+
 	default:
 	  /* xgettext:c-format */
 	  (*info-&gt;fprintf_func) (info-&gt;stream,
diff -burN binutils-2.16.1/opcodes/mips-opc.c binutils-psp/opcodes/mips-opc.c
--- binutils-2.16.1/opcodes/mips-opc.c	2005-03-03 11:49:50.000000000 +0000
+++ binutils-psp/opcodes/mips-opc.c	2006-05-09 02:55:36.000000000 +0100
@@ -109,6 +109,7 @@
 #define N5	(INSN_5400 | INSN_5500)
 #define N54	INSN_5400
 #define N55	INSN_5500
+#define AL	INSN_ALLEGREX
 
 #define G1      (T3             \
                  )
@@ -271,6 +272,7 @@
 {"bnel",    "s,t,p",	0x54000000, 0xfc000000,	CBL|RD_s|RD_t, 		0,		I2|T3	},
 {"bnel",    "s,I,p",	0,    (int) M_BNEL_I,	INSN_MACRO,		0,		I2|T3	},
 {"break",   "",		0x0000000d, 0xffffffff,	TRAP,			0,		I1	},
+{"break",   "B",	0x0000000d, 0xfc00003f,	TRAP,			0,		AL	},
 {"break",   "c",	0x0000000d, 0xfc00ffff,	TRAP,			0,		I1	},
 {"break",   "c,q",	0x0000000d, 0xfc00003f,	TRAP,			0,		I1	},
 {"c.f.d",   "S,T",	0x46200030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
@@ -432,7 +434,7 @@
 {"cabs.un.d",  "M,S,T",	0x46200071, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
 {"cabs.un.ps", "M,S,T",	0x46c00071, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
 {"cabs.un.s",  "M,S,T",	0x46000071, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,           	0,		I3|I32|T3},
+{"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,           	0,		I3|I32|T3|AL},
 {"ceil.l.d", "D,S",	0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3	},
 {"ceil.l.s", "D,S",	0x4600000a, 0xffff003f, WR_D|RD_S|FP_S,		0,		I3	},
 {"ceil.w.d", "D,S",	0x4620000e, 0xffff003f, WR_D|RD_S|FP_D,		0,		I2	},
@@ -443,7 +445,9 @@
 /* cfc2 is at the bottom of the table.  */
 {"cfc3",    "t,G",	0x4c400000, 0xffe007ff,	LCD|WR_t|RD_C3,		0,		I1	},
 {"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 	0,		I32|N55 },
+{"clo",     "d,s",      0x00000017, 0xfc1f07ff, WR_d|RD_s,      	0,		AL	},
 {"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 	0,		I32|N55 },
+{"clz",     "d,s",      0x00000016, 0xfc1f07ff, WR_d|RD_s,              0,              AL      },
 {"ctc0",    "t,G",	0x40c00000, 0xffe007ff,	COD|RD_t|WR_CC,		0,		I1	},
 {"ctc1",    "t,G",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	0,		I1	},
 {"ctc1",    "t,S",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	0,		I1	},
@@ -465,13 +469,15 @@
 {"cvt.ps.s","D,V,T",	0x46000026, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5	},
 {"cvt.pw.ps", "D,S",	0x46c00024, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		M3D	},
 {"dabs",    "d,v",	0,    (int) M_DABS,	INSN_MACRO,		0,		I3	},
+{"max",     "d,v,t",    0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              AL	},
 {"dadd",    "d,v,t",	0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I3	},
 {"dadd",    "t,r,I",	0,    (int) M_DADD_I,	INSN_MACRO,		0,		I3	},
 {"daddi",   "t,r,j",	0x60000000, 0xfc000000, WR_t|RD_s,		0,		I3	},
 {"daddiu",  "t,r,j",	0x64000000, 0xfc000000, WR_t|RD_s,		0,		I3	},
+{"min",     "d,v,t",    0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              AL	},
 {"daddu",   "d,v,t",	0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I3	},
 {"daddu",   "t,r,I",	0,    (int) M_DADDU_I,	INSN_MACRO,		0,		I3	},
-{"dbreak",  "",		0x7000003f, 0xffffffff,	0,			0,		N5	},
+{"dbreak",  "",		0x7000003f, 0xffffffff,	0,			0,		N5|AL	},
 {"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 	0,		I64|N55 },
 {"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 	0,		I64|N55 },
 /* dctr and dctw are used on the r5000.  */
@@ -558,7 +564,7 @@
 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
 {"dremu",   "d,v,t",	3,    (int) M_DREMU_3,	INSN_MACRO,		0,		I3	},
 {"dremu",   "d,v,I",	3,    (int) M_DREMU_3I,	INSN_MACRO,		0,		I3	},
-{"dret",    "",		0x7000003e, 0xffffffff,	0,			0,		N5	},
+{"dret",    "",		0x7000003e, 0xffffffff,	0,			0,		N5|AL	},
 {"drol",    "d,v,t",	0,    (int) M_DROL,	INSN_MACRO,		0,		I3	},
 {"drol",    "d,v,I",	0,    (int) M_DROL_I,	INSN_MACRO,		0,		I3	},
 {"dror",    "d,v,t",	0,    (int) M_DROR,	INSN_MACRO,		0,		I3	},
@@ -595,8 +601,8 @@
 {"dsubu",   "d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,		0,		I3	},
 {"ei",      "",		0x41606020, 0xffffffff,	WR_t|WR_C0,		0,		I33	},
 {"ei",      "t",	0x41606020, 0xffe0ffff,	WR_t|WR_C0,		0,		I33	},
-{"eret",    "",         0x42000018, 0xffffffff, 0,      		0,		I3|I32	},
-{"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,    		0,		I33	},
+{"eret",    "",         0x42000018, 0xffffffff, 0,      		0,		I3|I32|AL	},
+{"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,    		0,		I33|AL	},
 {"floor.l.d", "D,S",	0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3	},
 {"floor.l.s", "D,S",	0x4600000b, 0xffff003f, WR_D|RD_S|FP_S,		0,		I3	},
 {"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_D,		0,		I2	},
@@ -605,7 +611,7 @@
 {"flushd",  "",		0xbc020000, 0xffffffff, 0, 			0,		L1	},
 {"flushid", "",		0xbc030000, 0xffffffff, 0, 			0,		L1	},
 {"hibernate","",        0x42000023, 0xffffffff,	0, 			0,		V1	},
-{"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,    		0,		I33	},
+{"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,    		0,		I33|AL	},
 {"jr",      "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		0,		I1	},
 {"jr.hb",   "s",	0x00000408, 0xfc1fffff,	UBD|RD_s,		0,		I33	},
 {"j",       "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		0,		I1	}, /* jr */
@@ -639,18 +645,10 @@
 {"ld",	    "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,		0,		I3	},
 {"ld",      "t,o(b)",	0,    (int) M_LD_OB,	INSN_MACRO,		0,		I1	},
 {"ld",      "t,A(b)",	0,    (int) M_LD_AB,	INSN_MACRO,		0,		I1	},
-{"ldc1",    "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	},
-{"ldc1",    "E,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	},
-{"ldc1",    "T,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		0,		I2	},
-{"ldc1",    "E,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		0,		I2	},
-{"l.d",     "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	}, /* ldc1 */
-{"l.d",     "T,o(b)",	0,    (int) M_L_DOB,	INSN_MACRO,		0,		I1	},
-{"l.d",     "T,A(b)",	0,    (int) M_L_DAB,	INSN_MACRO,		0,		I1	},
-{"ldc2",    "E,o(b)",	0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,		0,		I2	},
-{"ldc2",    "E,A(b)",	0,    (int) M_LDC2_AB,	INSN_MACRO,		0,		I2	},
-{"ldc3",    "E,o(b)",	0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,		0,		I2	},
-{"ldc3",    "E,A(b)",	0,    (int) M_LDC3_AB,	INSN_MACRO,		0,		I2	},
-{"ldl",	    "t,o(b)",	0x68000000, 0xfc000000, LDD|WR_t|RD_b,		0,		I3	},
+/* ldc1 is at the bottom of the table.  */
+/* ldc2 is at the bottom of the table.  */
+/* ldc3 is at the bottom of the table.  */
+{"ldl",	    "t,o(b)",	0x68000000, 0xfc000000, LDD|WR_t|RD_b,		0,		I3|AL	},
 {"ldl",	    "t,A(b)",	0,    (int) M_LDL_AB,	INSN_MACRO,		0,		I3	},
 {"ldr",	    "t,o(b)",	0x6c000000, 0xfc000000, LDD|WR_t|RD_b,		0,		I3	},
 {"ldr",     "t,A(b)",	0,    (int) M_LDR_AB,	INSN_MACRO,		0,		I3	},
@@ -680,8 +678,7 @@
 {"lwc1",    "E,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		0,		I1	},
 {"l.s",     "T,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T|FP_S,	0,		I1	}, /* lwc1 */
 {"l.s",     "T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		0,		I1	},
-{"lwc2",    "E,o(b)",	0xc8000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1	},
-{"lwc2",    "E,A(b)",	0,    (int) M_LWC2_AB,	INSN_MACRO,		0,		I1	},
+/* lwc2 is at the bottom of the table.  */
 {"lwc3",    "E,o(b)",	0xcc000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1	},
 {"lwc3",    "E,A(b)",	0,    (int) M_LWC3_AB,	INSN_MACRO,		0,		I1	},
 {"lwl",     "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
@@ -713,10 +710,12 @@
 {"madd.s",  "D,R,S,T",	0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,		I4	},
 {"madd.ps", "D,R,S,T",	0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,		I5	},
 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,		L1 },
+{"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,         AL	},
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,		I32|N55},
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		G1 },
 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1 },
 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,		L1 },
+{"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,         AL	},
 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,		I32|N55},
 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		G1	},
 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
@@ -739,7 +738,7 @@
 /* mfhc2 is at the bottom of the table.  */
 {"mfc3",    "t,G",	0x4c000000, 0xffe007ff,	LCD|WR_t|RD_C3,		0,		I1	},
 {"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 	0,		I32     },
-{"mfdr",    "t,G",	0x7000003d, 0xffe007ff,	LCD|WR_t|RD_C0,		0,		N5      },
+{"mfdr",    "t,G",	0x7000003d, 0xffe007ff,	LCD|WR_t|RD_C0,		0,		N5|AL   },
 {"mfhi",    "d",	0x00000010, 0xffff07ff,	WR_d|RD_HI,		0,		I1	},
 {"mflo",    "d",	0x00000012, 0xffff07ff,	WR_d|RD_LO,		0,		I1	},
 {"min.ob",  "X,Y,Q",	0x78000006, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
@@ -756,7 +755,7 @@
 {"movf.l",  "X,Y,N",	0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		MX|SB1	},
 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,		I4|I32	},
 {"movf.ps", "D,S,N",	0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		I5	},
-{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		I4|I32	},
+{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		I4|I32|AL	},
 {"ffc",     "d,v",	0x0000000b, 0xfc1f07ff,	WR_d|RD_s,		0,		L1	},
 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I4|I32	},
 {"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		MX|SB1	},
@@ -769,7 +768,7 @@
 {"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,		MX|SB1	},
 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,		I4|I32	},
 {"movt.ps", "D,S,N",	0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		I5	},
-{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		I4|I32	},
+{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		I4|I32|AL	},
 {"ffs",     "d,v",	0x0000000a, 0xfc1f07ff,	WR_d|RD_s,		0,		L1	},
 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I4|I32	},
 {"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		MX|SB1	},
@@ -786,8 +785,10 @@
 {"msub.s",  "D,R,S,T",	0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,		I4	},
 {"msub.ps", "D,R,S,T",	0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I5	},
 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		L1    	},
+{"msub",    "s,t",      0x0000002e, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,              AL	},
 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		I32|N55 },
 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		L1	},
+{"msubu",   "s,t",      0x0000002f, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,              AL	},
 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		I32|N55	},
 {"mtpc",    "t,P",	0x4080c801, 0xffe0ffc1,	COD|RD_t|WR_C0,		0,		M1|N5	},
 {"mtps",    "t,P",	0x4080c800, 0xffe0ffc1,	COD|RD_t|WR_C0,		0,		M1|N5	},
@@ -802,7 +803,7 @@
 /* mthc2 is at the bottom of the table.  */
 {"mtc3",    "t,G",	0x4c800000, 0xffe007ff,	COD|RD_t|WR_C3|WR_CC,	0,		I1	},
 {"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,		I32     },
-{"mtdr",    "t,G",	0x7080003d, 0xffe007ff,	COD|RD_t|WR_C0,		0,		N5	},
+{"mtdr",    "t,G",	0x7080003d, 0xffe007ff,	COD|RD_t|WR_C0,		0,		N5|AL	},
 {"mthi",    "s",	0x00000011, 0xfc1fffff,	RD_s|WR_HI,		0,		I1	},
 {"mtlo",    "s",	0x00000013, 0xfc1fffff,	RD_s|WR_LO,		0,		I1	},
 {"mul.d",   "D,V,T",	0x46200002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
@@ -936,13 +937,13 @@
 {"rol",     "d,v,I",	0,    (int) M_ROL_I,	INSN_MACRO,		0,		I1	},
 {"ror",     "d,v,t",	0,    (int) M_ROR,	INSN_MACRO,		0,		I1	},
 {"ror",     "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO,		0,		I1	},
-{"ror",	    "d,w,&lt;",	0x00200002, 0xffe0003f,	WR_d|RD_t,		0,		N5|I33	},
-{"rorv",    "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,		0,		N5|I33	},
-{"rotl",    "d,v,t",	0,    (int) M_ROL,	INSN_MACRO,		0,		I33	},
-{"rotl",    "d,v,I",	0,    (int) M_ROL_I,	INSN_MACRO,		0,		I33	},
-{"rotr",    "d,v,t",	0,    (int) M_ROR,	INSN_MACRO,		0,		I33	},
-{"rotr",    "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO,		0,		I33	},
-{"rotrv",   "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,		0,		I33	},
+{"ror",	    "d,w,&lt;",	0x00200002, 0xffe0003f,	WR_d|RD_t,		0,		N5|I33|AL	},
+{"rorv",    "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,		0,		N5|I33|AL	},
+{"rotl",    "d,v,t",	0,    (int) M_ROL,	INSN_MACRO,		0,		I33|AL	},
+{"rotl",    "d,v,I",	0,    (int) M_ROL_I,	INSN_MACRO,		0,		I33|AL	},
+{"rotr",    "d,v,t",	0,    (int) M_ROR,	INSN_MACRO,		0,		I33|AL	},
+{"rotr",    "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO,		0,		I33|AL	},
+{"rotrv",   "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,		0,		I33|AL	},
 {"round.l.d", "D,S",	0x46200008, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3	},
 {"round.l.s", "D,S",	0x46000008, 0xffff003f, WR_D|RD_S|FP_S,		0,		I3	},
 {"round.w.d", "D,S",	0x4620000c, 0xffff003f, WR_D|RD_S|FP_D,		0,		I2	},
@@ -974,24 +975,17 @@
 {"sdbbp",   "c,q",	0x0000000e, 0xfc00003f,	TRAP,			0,		G2	},
 {"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,           	0,		I32     },
 {"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,           	0,		I32     },
-{"sdc1",    "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
-{"sdc1",    "E,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
-{"sdc1",    "T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		0,		I2	},
-{"sdc1",    "E,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		0,		I2	},
-{"sdc2",    "E,o(b)",	0xf8000000, 0xfc000000, SM|RD_C2|RD_b,		0,		I2	},
-{"sdc2",    "E,A(b)",	0,    (int) M_SDC2_AB,	INSN_MACRO,		0,		I2	},
-{"sdc3",    "E,o(b)",	0xfc000000, 0xfc000000, SM|RD_C3|RD_b,		0,		I2	},
-{"sdc3",    "E,A(b)",	0,    (int) M_SDC3_AB,	INSN_MACRO,		0,		I2	},
-{"s.d",     "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
-{"s.d",     "T,o(b)",	0,    (int) M_S_DOB,	INSN_MACRO,		0,		I1	},
-{"s.d",     "T,A(b)",	0,    (int) M_S_DAB,	INSN_MACRO,		0,		I1	},
-{"sdl",     "t,o(b)",	0xb0000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I3	},
+/* sdc1 is at the bottom of the table.  */
+/* sdc2 is at the bottom of the table.  */
+/* sdc3 is at the bottom of the table.  */
+/* s.d (sdc1 is at the bottom of the table.  */
+{"sdl",     "t,o(b)",	0xb0000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I3|AL	},
 {"sdl",     "t,A(b)",	0,    (int) M_SDL_AB,	INSN_MACRO,		0,		I3	},
 {"sdr",     "t,o(b)",	0xb4000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I3	},
 {"sdr",     "t,A(b)",	0,    (int) M_SDR_AB,	INSN_MACRO,		0,		I3	},
 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b,	0,		I4	},
-{"seb",     "d,w",	0x7c000420, 0xffe007ff,	WR_d|RD_t,		0,		I33	},
-{"seh",     "d,w",	0x7c000620, 0xffe007ff,	WR_d|RD_t,		0,		I33	},
+{"seb",     "d,w",	0x7c000420, 0xffe007ff,	WR_d|RD_t,		0,		I33|AL	},
+{"seh",     "d,w",	0x7c000620, 0xffe007ff,	WR_d|RD_t,		0,		I33|AL	},
 {"selsl",   "d,v,t",	0x00000005, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		L1	},
 {"selsr",   "d,v,t",	0x00000001, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		L1	},
 {"seq",     "d,v,t",	0,    (int) M_SEQ,	INSN_MACRO,		0,		I1	},
@@ -1083,8 +1077,7 @@
 {"swc1",    "E,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		0,		I1	},
 {"s.s",     "T,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	0,		I1	}, /* swc1 */
 {"s.s",     "T,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		0,		I1	},
-{"swc2",    "E,o(b)",	0xe8000000, 0xfc000000,	SM|RD_C2|RD_b,		0,		I1	},
-{"swc2",    "E,A(b)",	0,    (int) M_SWC2_AB,	INSN_MACRO,		0,		I1	},
+/* swc2 is at the bottom of the table.  */
 {"swc3",    "E,o(b)",	0xec000000, 0xfc000000,	SM|RD_C3|RD_b,		0,		I1	},
 {"swc3",    "E,A(b)",	0,    (int) M_SWC3_AB,	INSN_MACRO,		0,		I1	},
 {"swl",     "t,o(b)",	0xa8000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
@@ -1169,7 +1162,8 @@
 {"waiti",   "",		0x42000020, 0xffffffff,	TRAP,			0,		L1	},
 {"wb", 	    "o(b)",	0xbc040000, 0xfc1f0000, SM|RD_b,		0,		L1	},
 {"wrpgpr",  "d,w",	0x41c00000, 0xffe007ff, RD_t,			0,		I33	},
-{"wsbh",    "d,w",	0x7c0000a0, 0xffe007ff,	WR_d|RD_t,		0,		I33	},
+{"wsbh",    "d,w",	0x7c0000a0, 0xffe007ff,	WR_d|RD_t,		0,		I33|AL	},
+{"wsbw",    "d,t",	0x7c0000e0, 0xffe007ff, WR_d|RD_t,		0,		AL	},
 {"xor",     "d,v,t",	0x00000026, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"xor",     "t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,		0,		I1	},
 {"xor.ob",  "X,Y,Q",	0x7800000d, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
@@ -1179,6 +1173,319 @@
 {"xor.qh",  "X,Y,Q",	0x7820000d, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
 {"xori",    "t,r,i",	0x38000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
 
+/* Sony Allegrex CPU core.  */
+{"bitrev",  "d,t",      0x7c000520, 0xffe007ff, WR_d|RD_t,              0,              AL	},
+{"mfic",    "t,G",	0x70000024, 0xffe007ff, LCD|WR_t|RD_C0,		0,		AL	},
+{"mtic",    "t,G",	0x70000026, 0xffe007ff, COD|RD_t|WR_C0,		0,		AL	},
+
+/* Sony Allegrex VFPU instructions.  */
+{"bvf",     "?c,p",		0x49000000, 0xffe30000, CBD|RD_CC,	0,		AL	},
+{"bvfl",    "?c,p",		0x49020000, 0xffe30000, CBL|RD_CC,	0,		AL	},
+{"bvt",     "?c,p",		0x49010000, 0xffe30000, CBD|RD_CC,	0,		AL	},
+{"bvtl",    "?c,p",		0x49030000, 0xffe30000, CBL|RD_CC,	0,		AL	},
+{"lv.s",    "?m0x,?o(b)",	0xc8000000, 0xfc000000, CLD|RD_s|WR_CC,	0,		AL	},
+{"lv.s",    "?m0x,A(b)",	0,    (int) M_LV_Q_AB,	INSN_MACRO,	0,		AL	},
+{"ulv.s",   "?m0x,o(b)",	0,    (int) M_ULV_S,	INSN_MACRO,	0,		AL	},
+{"lv.q",    "?n3x,?o(b)",	0xd8000000, 0xfc000002, CLD|RD_s|WR_CC,	0,		AL	},
+{"lv.q",    "?n3x,A(b)",	0,    (int) M_LV_Q_AB_2,	INSN_MACRO,	0,	AL	},
+{"ulv.q",   "?n3x,?o(b)",	0,    (int) M_ULV_Q,	INSN_MACRO,	0,		AL	},
+{"ulv.q",   "?n3x,A(b)",	0,    (int) M_ULV_Q_AB,	INSN_MACRO,	0,		AL	},
+{"lvi.s",   "?t0x,l?y0",	0,    (int) M_LVI_S,	INSN_MACRO,	0,		AL	},
+{"lvi.p",   "?t1x,?[l?y0,l?y1?]", 0,  (int) M_LVI_P,	INSN_MACRO,	0,		AL	},
+{"lvi.t",   "?t2x,?[l?y0,l?y1,l?y2?]", 0, (int) M_LVI_T,	INSN_MACRO,	0,	AL	},
+{"lvi.q",   "?t3x,?[l?y0,l?y1,l?y2,l?y3?]", 0, (int) M_LVI_Q,	INSN_MACRO,	0,	AL	},
+{"lvhi.s",  "?t0x,?[?u?y0,?u?y1?]", 0, (int) M_LVHI_S,	INSN_MACRO,	0,		AL	},
+{"lvhi.p",  "?t1x,?[?u?y0,?u?y1,?u?y2,?u?y3?]", 0, (int) M_LVHI_P,	INSN_MACRO, 0,	AL	},
+{"sv.s",    "?m0x,?o(b)",	0xe8000000, 0xfc000000, SM|RD_s|RD_C2,	0,		AL	},
+{"sv.s",    "?m0x,A(b)",	0,    (int) M_SV_S_AB,	INSN_MACRO,	0,		AL	},
+{"usv.s",   "?m0x,o(b)",	0,    (int) M_USV_S,	INSN_MACRO,	0,		AL	},
+{"sv.q",    "?n3x,?o(b)",	0xf8000000, 0xfc000002, SM|RD_s|RD_C2,	0,		AL	},
+{"sv.q",    "?n3x,?o(b),?z",	0xf8000000, 0xfc000000, SM|RD_s|RD_C2,	0,		AL	},
+{"sv.q",    "?n3x,A(b)",	0,    (int) M_SV_Q_AB,	INSN_MACRO,	0,		AL	},
+{"sv.q",    "?n3x,A(b),?z",	0,    (int) M_SV_Q_AB,	INSN_MACRO,	0,		AL	},
+{"sv.q",    "?n3x,A,?z",	0,    (int) M_SV_Q_AB,	INSN_MACRO,	0,		AL	},
+{"usv.q",   "?n3x,?o(b)",	0,    (int) M_USV_Q,	INSN_MACRO,	0,		AL	},
+{"usv.q",   "?n3x,A(b)",	0,    (int) M_USV_Q_AB,	INSN_MACRO,	0,		AL	},
+{"vwb.q",   "?n3x,?o(b)",	0xf8000002, 0xfc000002, SM|RD_s|RD_C2,	0,		AL	},
+{"lvl.q",   "?n3x,?o(b)",	0xd4000000, 0xfc000002, CLD|RD_s|WR_CC,	0,		AL	},
+{"lvl.q",   "?n3x,A(b)",	0,    (int) M_LVL_Q_AB,	INSN_MACRO,	0,		AL	},
+{"lvr.q",   "?n3x,?o(b)",	0xd4000002, 0xfc000002, CLD|RD_s|WR_CC,	0,		AL	},
+{"lvr.q",   "?n3x,A(b)",	0,    (int) M_LVR_Q_AB,	INSN_MACRO,	0,		AL	},
+{"svl.q",   "?n3x,?o(b)",	0xf4000000, 0xfc000002, SM|RD_s|RD_C2,	0,		AL	},
+{"svl.q",   "?n3x,A(b)",	0,    (int) M_SVL_Q_AB,	INSN_MACRO,	0,		AL	},
+{"svr.q",   "?n3x,?o(b)",	0xf4000002, 0xfc000002, SM|RD_s|RD_C2,	0,		AL	},
+{"svr.q",   "?n3x,A(b)",	0,    (int) M_SVR_Q_AB,	INSN_MACRO,	0,		AL	},
+{"mtv",     "t,?d0z",		0x48e00000, 0xffe0ff80, LCD|WR_t|WR_C2,	0,		AL	},
+{"mfv",     "t,?d0z",		0x48600000, 0xffe0ff80, COD|RD_t|WR_CC|RD_C2, 0,	AL	},
+{"mtvc",    "t,?q",		0x48e00000, 0xffe0ff00, LCD|WR_t|WR_C2,	0,		AL	},
+{"mfvc",    "t,?q",		0x48600000, 0xffe0ff00, COD|RD_t|WR_CC|RD_C2, 0,	AL	},
+{"vmtvc",   "?q,?s0y",		0xd0510000, 0xffff8000, WR_C2,		0,		AL	},
+{"vmfvc",   "?d0z,?r",		0xd0500000, 0xffff0080, RD_C2,		0,		AL	},
+{"vadd.q",  "?d3d,?s3s,?t3t",	0x60008080, 0xff808080, RD_C2,		0,		AL	},
+{"vsub.q",  "?d3d,?s3s,?t3t",	0x60808080, 0xff808080, RD_C2,		0,		AL	},
+{"vdiv.q",  "?x3z,?s3y,?t3x",	0x63808080, 0xff808080, RD_C2,		0,		AL	},
+{"vmul.q",  "?d3d,?s3s,?t3t",	0x64008080, 0xff808080, RD_C2,		0,		AL	},
+{"vdot.q",  "?d0d,?s3s,?t3t",	0x64808080, 0xff808080, RD_C2,		0,		AL	},
+{"vscl.q",  "?d3d,?s3s,?t0x",	0x65008080, 0xff808080, RD_C2,		0,		AL	},
+{"vhdp.q",  "?d0d,?s3y,?t3t",	0x66008080, 0xff808080, RD_C2,		0,		AL	},
+{"vcmp.q",  "?f2,?s3s,?t3t",	0x6c008080, 0xff8080f0, RD_C2,		0,		AL	},
+{"vcmp.q",  "?f1,?s3s",		0x6c008080, 0xffff80f0, RD_C2,		0,		AL	},
+{"vcmp.q",  "?f0",		0x6c008080, 0xfffffff0, RD_C2,		0,		AL	},
+{"vmin.q",  "?d3d,?s3s,?t3t",	0x6d008080, 0xff808080, RD_C2,		0,		AL	},
+{"vmax.q",  "?d3d,?s3s,?t3t",	0x6d808080, 0xff808080, RD_C2,		0,		AL	},
+{"vsgn.q",  "?d3d,?s3s",	0xd04a8080, 0xffff8080, RD_C2,		0,		AL	},
+{"vcst.q",  "?d3d,?a",		0xd0608080, 0xffe0ff80, RD_C2,		0,		AL	},
+{"vscmp.q", "?d3d,?s3s,?t3t",	0x6e808080, 0xff808080, RD_C2,		0,		AL	},
+{"vsge.q",  "?d3d,?s3s,?t3t",	0x6f008080, 0xff808080, RD_C2,		0,		AL	},
+{"vslt.q",  "?d3d,?s3s,?t3t",	0x6f808080, 0xff808080, RD_C2,		0,		AL	},
+{"vi2uc.q", "?d0m,?s3w",	0xd03c8080, 0xffff8080, RD_C2,		0,		AL	},
+{"vi2c.q",  "?d0m,?s3w",	0xd03d8080, 0xffff8080, RD_C2,		0,		AL	},
+{"vi2us.q", "?d1m,?s3w",	0xd03e8080, 0xffff8080, RD_C2,		0,		AL	},
+{"vi2s.q",  "?d1m,?s3w",	0xd03f8080, 0xffff8080, RD_C2,		0,		AL	},
+{"vmov.q",  "?d3d,?s3s",	0xd0008080, 0xffff8080, RD_C2,		0,		AL	},
+{"vabs.q",  "?d3d,?s3w",	0xd0018080, 0xffff8080, RD_C2,		0,		AL	},
+{"vneg.q",  "?d3d,?s3w",	0xd0028080, 0xffff8080, RD_C2,		0,		AL	},
+{"vidt.q",  "?d3d",		0xd0038080, 0xffffff80, RD_C2,		0,		AL	},
+{"vsat0.q", "?d3z,?s3s",	0xd0048080, 0xffff8080, RD_C2,		0,		AL	},
+{"vsat1.q", "?d3z,?s3s",	0xd0058080, 0xffff8080, RD_C2,		0,		AL	},
+{"vzero.q", "?d3d",		0xd0068080, 0xffffff80, RD_C2,		0,		AL	},
+{"vone.q",  "?d3d",		0xd0078080, 0xffffff80, RD_C2,		0,		AL	},
+{"vrcp.q",  "?x3z,?s3y",	0xd0108080, 0xffff8080, RD_C2,		0,		AL	},
+{"vrsq.q",  "?x3z,?s3y",	0xd0118080, 0xffff8080, RD_C2,		0,		AL	},
+{"vsin.q",  "?x3z,?s3y",	0xd0128080, 0xffff8080, RD_C2,		0,		AL	},
+{"vcos.q",  "?x3z,?s3y",	0xd0138080, 0xffff8080, RD_C2,		0,		AL	},
+{"vexp2.q", "?x3z,?s3y",	0xd0148080, 0xffff8080, RD_C2,		0,		AL	},
+{"vlog2.q", "?x3z,?s3y",	0xd0158080, 0xffff8080, RD_C2,		0,		AL	},
+{"vsqrt.q", "?x3z,?s3y",	0xd0168080, 0xffff8080, RD_C2,		0,		AL	},
+{"vasin.q", "?x3z,?s3y",	0xd0178080, 0xffff8080, RD_C2,		0,		AL	},
+{"vnrcp.q", "?x3z,?s3y",	0xd0188080, 0xffff8080, RD_C2,		0,		AL	},
+{"vnsin.q", "?x3z,?s3y",	0xd01a8080, 0xffff8080, RD_C2,		0,		AL	},
+{"vrexp2.q", "?x3z,?s3y",	0xd01c8080, 0xffff8080, RD_C2,		0,		AL	},
+{"vrndi.q", "?d3z",		0xd0218080, 0xffffff80, RD_C2,		0,		AL	},
+{"vrndf1.q", "?d3z",		0xd0228080, 0xffffff80, RD_C2,		0,		AL	},
+{"vrndf2.q", "?d3z",		0xd0238080, 0xffffff80, RD_C2,		0,		AL	},
+{"vf2h.q",  "?d1m,?s3s",	0xd0328080, 0xffff8080, RD_C2,		0,		AL	},
+{"vsrt1.q", "?d3d,?s3s",	0xd0408080, 0xffff8080, RD_C2,		0,		AL	},
+{"vsrt2.q", "?d3d,?s3s",	0xd0418080, 0xffff8080, RD_C2,		0,		AL	},
+{"vsrt3.q", "?d3d,?s3s",	0xd0488080, 0xffff8080, RD_C2,		0,		AL	},
+{"vsrt4.q", "?d3d,?s3s",	0xd0498080, 0xffff8080, RD_C2,		0,		AL	},
+{"vbfy1.q", "?d3d,?s3s",	0xd0428080, 0xffff8080, RD_C2,		0,		AL	},
+{"vbfy2.q", "?d3d,?s3s",	0xd0438080, 0xffff8080, RD_C2,		0,		AL	},
+{"vocp.q",  "?d3d,?s3y",	0xd0448080, 0xffff8080, RD_C2,		0,		AL	},
+{"vfad.q",  "?d0d,?s3s",	0xd0468080, 0xffff8080, RD_C2,		0,		AL	},
+{"vavg.q",  "?d0d,?s3s",	0xd0478080, 0xffff8080, RD_C2,		0,		AL	},
+{"vf2in.q", "?d3m,?s3s,?b",	0xd2008080, 0xffe08080, RD_C2,		0,		AL	},
+{"vf2iz.q", "?d3m,?s3s,?b",	0xd2208080, 0xffe08080, RD_C2,		0,		AL	},
+{"vf2iu.q", "?d3m,?s3s,?b",	0xd2408080, 0xffe08080, RD_C2,		0,		AL	},
+{"vf2id.q", "?d3m,?s3s,?b",	0xd2608080, 0xffe08080, RD_C2,		0,		AL	},
+{"vi2f.q",  "?d3d,?s3w,?b",	0xd2808080, 0xffe08080, RD_C2,		0,		AL	},
+{"vcmov.q", "?d3d,?s3s,?e",	0,    (int) M_VCMOV_Q,	INSN_MACRO,	0,		AL	},
+{"vcmovt.q", "?d3d,?s3s,?e",	0xd2a08080, 0xfff88080, RD_C2,		0,		AL	},
+{"vcmovf.q", "?d3d,?s3s,?e",	0xd2a88080, 0xfff88080, RD_C2,		0,		AL	},
+{"vmmul.q", "?v7z,?s7y,?t7x",	0xf0008080, 0xff808080, RD_C2,		0,		AL	},
+{"vtfm4.q", "?v3z,?s7y,?t3x",	0xf1808080, 0xff808080, RD_C2,		0,		AL	},
+{"vhtfm4.q", "?v3z,?s7y,?t3x",	0xf1808000, 0xff808080, RD_C2,		0,		AL	},
+{"vmscl.q", "?x7z,?s7y,?t0x",	0xf2008080, 0xff808080, RD_C2,		0,		AL	},
+{"vqmul.q", "?v3z,?s3y,?t3x",	0xf2808080, 0xff808080, RD_C2,		0,		AL	},
+{"vmmov.q", "?x7z,?s7y",	0xf3808080, 0xffff8080, RD_C2,		0,		AL	},
+{"vmidt.q", "?d7z",		0xf3838080, 0xffffff80, RD_C2,		0,		AL	},
+{"vmzero.q", "?d7z",		0xf3868080, 0xffffff80, RD_C2,		0,		AL	},
+{"vmone.q", "?d7z",		0xf3878080, 0xffffff80, RD_C2,		0,		AL	},
+{"vrot.q",  "?x3z,?s0y,?w",	0xf3a08080, 0xffe08080, RD_C2,		0,		AL	},
+{"vt4444.q", "?d1z,?s3w",	0xd0598080, 0xffff8080, RD_C2,		0,		AL	},
+{"vt5551.q", "?d1z,?s3w",	0xd05a8080, 0xffff8080, RD_C2,		0,		AL	},
+{"vt5650.q", "?d1z,?s3w",	0xd05b8080, 0xffff8080, RD_C2,		0,		AL	},
+{"vadd.t",  "?d2d,?s2s,?t2t",	0x60008000, 0xff808080, RD_C2,		0,		AL	},
+{"vsub.t",  "?d2d,?s2s,?t2t",	0x60808000, 0xff808080, RD_C2,		0,		AL	},
+{"vdiv.t",  "?x2z,?s2y,?t2x",	0x63808000, 0xff808080, RD_C2,		0,		AL	},
+{"vmul.t",  "?d2d,?s2s,?t2t",	0x64008000, 0xff808080, RD_C2,		0,		AL	},
+{"vdot.t",  "?d0d,?s2s,?t2t",	0x64808000, 0xff808080, RD_C2,		0,		AL	},
+{"vscl.t",  "?d2d,?s2s,?t0x",	0x65008000, 0xff808080, RD_C2,		0,		AL	},
+{"vhdp.t",  "?d0d,?s2y,?t2t",	0x66008000, 0xff808080, RD_C2,		0,		AL	},
+{"vcrs.t",  "?d2d,?s2y,?t2x",	0x66808000, 0xff808080, RD_C2,		0,		AL	},
+{"vcmp.t",  "?f2,?s2s,?t2t",	0x6c008000, 0xff8080f0, RD_C2,		0,		AL	},
+{"vcmp.t",  "?f1,?s2s",		0x6c008000, 0xffff80f0, RD_C2,		0,		AL	},
+{"vcmp.t",  "?f0",		0x6c008000, 0xfffffff0, RD_C2,		0,		AL	},
+{"vmin.t",  "?d2d,?s2s,?t2t",	0x6d008000, 0xff808080, RD_C2,		0,		AL	},
+{"vmax.t",  "?d2d,?s2s,?t2t",	0x6d808000, 0xff808080, RD_C2,		0,		AL	},
+{"vsgn.t",  "?d2d,?s2s",	0xd04a8000, 0xffff8080, RD_C2,		0,		AL	},
+{"vcst.t",  "?d2d,?a",		0xd0608000, 0xffe0ff80, RD_C2,		0,		AL	},
+{"vscmp.t", "?d2d,?s2s,?t2t",	0x6e808000, 0xff808080, RD_C2,		0,		AL	},
+{"vsge.t",  "?d2d,?s2s,?t2t",	0x6f008000, 0xff808080, RD_C2,		0,		AL	},
+{"vslt.t",  "?d2d,?s2s,?t2t",	0x6f808000, 0xff808080, RD_C2,		0,		AL	},
+{"vmov.t",  "?d2d,?s2s",	0xd0008000, 0xffff8080, RD_C2,		0,		AL	},
+{"vabs.t",  "?d2d,?s2w",	0xd0018000, 0xffff8080, RD_C2,		0,		AL	},
+{"vneg.t",  "?d2d,?s2w",	0xd0028000, 0xffff8080, RD_C2,		0,		AL	},
+{"vsat0.t", "?d2z,?s2s",	0xd0048000, 0xffff8080, RD_C2,		0,		AL	},
+{"vsat1.t", "?d2z,?s2s",	0xd0058000, 0xffff8080, RD_C2,		0,		AL	},
+{"vzero.t", "?d2d",		0xd0068000, 0xffffff80, RD_C2,		0,		AL	},
+{"vone.t",  "?d2d",		0xd0078000, 0xffffff80, RD_C2,		0,		AL	},
+{"vrcp.t",  "?x2z,?s2y",	0xd0108000, 0xffff8080, RD_C2,		0,		AL	},
+{"vrsq.t",  "?x2z,?s2y",	0xd0118000, 0xffff8080, RD_C2,		0,		AL	},
+{"vsin.t",  "?x2z,?s2y",	0xd0128000, 0xffff8080, RD_C2,		0,		AL	},
+{"vcos.t",  "?x2z,?s2y",	0xd0138000, 0xffff8080, RD_C2,		0,		AL	},
+{"vexp2.t", "?x2z,?s2y",	0xd0148000, 0xffff8080, RD_C2,		0,		AL	},
+{"vlog2.t", "?x2z,?s2y",	0xd0158000, 0xffff8080, RD_C2,		0,		AL	},
+{"vsqrt.t", "?x2z,?s2y",	0xd0168000, 0xffff8080, RD_C2,		0,		AL	},
+{"vasin.t", "?x2z,?s2y",	0xd0178000, 0xffff8080, RD_C2,		0,		AL	},
+{"vnrcp.t", "?x2z,?s2y",	0xd0188000, 0xffff8080, RD_C2,		0,		AL	},
+{"vnsin.t", "?x2z,?s2y",	0xd01a8000, 0xffff8080, RD_C2,		0,		AL	},
+{"vrexp2.t", "?x2z,?s2y",	0xd01c8000, 0xffff8080, RD_C2,		0,		AL	},
+{"vrndi.t", "?d2z",		0xd0218000, 0xffffff80, RD_C2,		0,		AL	},
+{"vrndf1.t", "?d2z",		0xd0228000, 0xffffff80, RD_C2,		0,		AL	},
+{"vrndf2.t", "?d2z",		0xd0238000, 0xffffff80, RD_C2,		0,		AL	},
+{"vocp.t",  "?d2d,?s2y",	0xd0448000, 0xffff8080, RD_C2,		0,		AL	},
+{"vfad.t",  "?d0d,?s2s",	0xd0468000, 0xffff8080, RD_C2,		0,		AL	},
+{"vavg.t",  "?d0d,?s2s",	0xd0478000, 0xffff8080, RD_C2,		0,		AL	},
+{"vf2in.t", "?d2m,?s2s,?b",	0xd2008000, 0xffe08080, RD_C2,		0,		AL	},
+{"vf2iz.t", "?d2m,?s2s,?b",	0xd2208000, 0xffe08080, RD_C2,		0,		AL	},
+{"vf2iu.t", "?d2m,?s2s,?b",	0xd2408000, 0xffe08080, RD_C2,		0,		AL	},
+{"vf2id.t", "?d2m,?s2s,?b",	0xd2608000, 0xffe08080, RD_C2,		0,		AL	},
+{"vi2f.t",  "?d2d,?s2w,?b",	0xd2808000, 0xffe08080, RD_C2,		0,		AL	},
+{"vcmov.t", "?d2d,?s2s,?e",	0,    (int) M_VCMOV_T,	INSN_MACRO,	0,		AL	},
+{"vcmovt.t", "?d2d,?s2s,?e",	0xd2a08000, 0xfff88080, RD_C2,		0,		AL	},
+{"vcmovf.t", "?d2d,?s2s,?e",	0xd2a88000, 0xfff88080, RD_C2,		0,		AL	},
+{"vmmul.t", "?v6z,?s6y,?t6x",	0xf0008000, 0xff808080, RD_C2,		0,		AL	},
+{"vtfm3.t", "?v2z,?s6y,?t2x",	0xf1008000, 0xff808080, RD_C2,		0,		AL	},
+{"vhtfm3.t", "?v2z,?s6y,?t2x",	0xf1000080, 0xff808080, RD_C2,		0,		AL	},
+{"vmscl.t", "?x6z,?s6y,?t0x",	0xf2008000, 0xff808080, RD_C2,		0,		AL	},
+{"vmmov.t", "?x6z,?s6y",	0xf3808000, 0xffff8080, RD_C2,		0,		AL	},
+{"vmidt.t", "?d6z",		0xf3838000, 0xffffff80, RD_C2,		0,		AL	},
+{"vmzero.t", "?d6z",		0xf3868000, 0xffffff80, RD_C2,		0,		AL	},
+{"vmone.t", "?d6z",		0xf3878000, 0xffffff80, RD_C2,		0,		AL	},
+{"vrot.t",  "?x2z,?s0y,?w",	0xf3a08000, 0xffe08080, RD_C2,		0,		AL	},
+{"vcrsp.t", "?d2z,?s2y,?t2x",	0xf2808000, 0xff808080, RD_C2,		0,		AL	},
+{"vadd.p",  "?d1d,?s1s,?t1t",	0x60000080, 0xff808080, RD_C2,		0,		AL	},
+{"vsub.p",  "?d1d,?s1s,?t1t",	0x60800080, 0xff808080, RD_C2,		0,		AL	},
+{"vdiv.p",  "?x1z,?s1y,?t1x",	0x63800080, 0xff808080, RD_C2,		0,		AL	},
+{"vmul.p",  "?d1d,?s1s,?t1t",	0x64000080, 0xff808080, RD_C2,		0,		AL	},
+{"vdot.p",  "?d0d,?s1s,?t1t",	0x64800080, 0xff808080, RD_C2,		0,		AL	},
+{"vscl.p",  "?d1d,?s1s,?t0x",	0x65000080, 0xff808080, RD_C2,		0,		AL	},
+{"vhdp.p",  "?d0d,?s1y,?t1t",	0x66000080, 0xff808080, RD_C2,		0,		AL	},
+{"vdet.p",  "?d0d,?s1s,?t1x",	0x67000080, 0xff808080, RD_C2,		0,		AL	},
+{"vcmp.p",  "?f2,?s1s,?t1t",	0x6c000080, 0xff8080f0, RD_C2,		0,		AL	},
+{"vcmp.p",  "?f1,?s1s",		0x6c000080, 0xffff80f0, RD_C2,		0,		AL	},
+{"vcmp.p",  "?f0",		0x6c000080, 0xfffffff0, RD_C2,		0,		AL	},
+{"vmin.p",  "?d1d,?s1s,?t1t",	0x6d000080, 0xff808080, RD_C2,		0,		AL	},
+{"vmax.p",  "?d1d,?s1s,?t1t",	0x6d800080, 0xff808080, RD_C2,		0,		AL	},
+{"vsgn.p",  "?d1d,?s1s",	0xd04a0080, 0xffff8080, RD_C2,		0,		AL	},
+{"vcst.p",  "?d1d,?a",		0xd0600080, 0xffe0ff80, RD_C2,		0,		AL	},
+{"vscmp.p", "?d1d,?s1s,?t1t",	0x6e800080, 0xff808080, RD_C2,		0,		AL	},
+{"vsge.p",  "?d1d,?s1s,?t1t",	0x6f000080, 0xff808080, RD_C2,		0,		AL	},
+{"vslt.p",  "?d1d,?s1s,?t1t",	0x6f800080, 0xff808080, RD_C2,		0,		AL	},
+{"vus2i.p", "?d3m,?s1y",	0xd03a0080, 0xffff8080, RD_C2,		0,		AL	},
+{"vs2i.p",  "?d3m,?s1y",	0xd03b0080, 0xffff8080, RD_C2,		0,		AL	},
+{"vi2us.p", "?d0m,?s1w",	0xd03e0080, 0xffff8080, RD_C2,		0,		AL	},
+{"vi2s.p",  "?d0m,?s1w",	0xd03f0080, 0xffff8080, RD_C2,		0,		AL	},
+{"vmov.p",  "?d1d,?s1s",	0xd0000080, 0xffff8080, RD_C2,		0,		AL	},
+{"vabs.p",  "?d1d,?s1w",	0xd0010080, 0xffff8080, RD_C2,		0,		AL	},
+{"vneg.p",  "?d1d,?s1w",	0xd0020080, 0xffff8080, RD_C2,		0,		AL	},
+{"vidt.p",  "?d1d",		0xd0030080, 0xffffff80, RD_C2,		0,		AL	},
+{"vsat0.p", "?d1z,?s1s",	0xd0040080, 0xffff8080, RD_C2,		0,		AL	},
+{"vsat1.p", "?d1z,?s1s",	0xd0050080, 0xffff8080, RD_C2,		0,		AL	},
+{"vzero.p", "?d1d",		0xd0060080, 0xffffff80, RD_C2,		0,		AL	},
+{"vone.p",  "?d1d",		0xd0070080, 0xffffff80, RD_C2,		0,		AL	},
+{"vrcp.p",  "?x1z,?s1y",	0xd0100080, 0xffff8080, RD_C2,		0,		AL	},
+{"vrsq.p",  "?x1z,?s1y",	0xd0110080, 0xffff8080, RD_C2,		0,		AL	},
+{"vsin.p",  "?x1z,?s1y",	0xd0120080, 0xffff8080, RD_C2,		0,		AL	},
+{"vcos.p",  "?x1z,?s1y",	0xd0130080, 0xffff8080, RD_C2,		0,		AL	},
+{"vexp2.p", "?x1z,?s1y",	0xd0140080, 0xffff8080, RD_C2,		0,		AL	},
+{"vlog2.p", "?x1z,?s1y",	0xd0150080, 0xffff8080, RD_C2,		0,		AL	},
+{"vsqrt.p", "?x1z,?s1y",	0xd0160080, 0xffff8080, RD_C2,		0,		AL	},
+{"vasin.p", "?x1z,?s1y",	0xd0170080, 0xffff8080, RD_C2,		0,		AL	},
+{"vnrcp.p", "?x1z,?s1y",	0xd0180080, 0xffff8080, RD_C2,		0,		AL	},
+{"vnsin.p", "?x1z,?s1y",	0xd01a0080, 0xffff8080, RD_C2,		0,		AL	},
+{"vrexp2.p", "?x1z,?s1y",	0xd01c0080, 0xffff8080, RD_C2,		0,		AL	},
+{"vrndi.p", "?d1z",		0xd0210080, 0xffffff80, RD_C2,		0,		AL	},
+{"vrndf1.p", "?d1z",		0xd0220080, 0xffffff80, RD_C2,		0,		AL	},
+{"vrndf2.p", "?d1z",		0xd0230080, 0xffffff80, RD_C2,		0,		AL	},
+{"vf2h.p",  "?d0m,?s1s",	0xd0320080, 0xffff8080, RD_C2,		0,		AL	},
+{"vh2f.p",  "?d3d,?s1y",	0xd0330080, 0xffff8080, RD_C2,		0,		AL	},
+{"vbfy1.p", "?d1d,?s1s",	0xd0420080, 0xffff8080, RD_C2,		0,		AL	},
+{"vocp.p",  "?d1d,?s1y",	0xd0440080, 0xffff8080, RD_C2,		0,		AL	},
+{"vsocp.p", "?d3z,?s1y",	0xd0450080, 0xffff8080, RD_C2,		0,		AL	},
+{"vfad.p",  "?d0d,?s1s",	0xd0460080, 0xffff8080, RD_C2,		0,		AL	},
+{"vavg.p",  "?d0d,?s1s",	0xd0470080, 0xffff8080, RD_C2,		0,		AL	},
+{"vf2in.p", "?d1m,?s1s,?b",	0xd2000080, 0xffe08080, RD_C2,		0,		AL	},
+{"vf2iz.p", "?d1m,?s1s,?b",	0xd2200080, 0xffe08080, RD_C2,		0,		AL	},
+{"vf2iu.p", "?d1m,?s1s,?b",	0xd2400080, 0xffe08080, RD_C2,		0,		AL	},
+{"vf2id.p", "?d1m,?s1s,?b",	0xd2600080, 0xffe08080, RD_C2,		0,		AL	},
+{"vi2f.p",  "?d1d,?s1w,?b",	0xd2800080, 0xffe08080, RD_C2,		0,		AL	},
+{"vcmov.p", "?d1d,?s1s,?e",	0,    (int) M_VCMOV_P,	INSN_MACRO,	0,		AL	},
+{"vcmovt.p", "?d1d,?s1s,?e",	0xd2a00080, 0xfff88080, RD_C2,		0,		AL	},
+{"vcmovf.p", "?d1d,?s1s,?e",	0xd2a80080, 0xfff88080, RD_C2,		0,		AL	},
+{"vmmul.p", "?v5z,?s5y,?t5x",	0xf0000080, 0xff808080, RD_C2,		0,		AL	},
+{"vtfm2.p", "?v1z,?s5y,?t1x",	0xf0800080, 0xff808080, RD_C2,		0,		AL	},
+{"vhtfm2.p", "?v1z,?s5y,?t1x",	0xf0800000, 0xff808080, RD_C2,		0,		AL	},
+{"vmscl.p", "?x5z,?s5y,?t0x",	0xf2000080, 0xff808080, RD_C2,		0,		AL	},
+{"vmmov.p", "?x5z,?s5y",	0xf3800080, 0xffff8080, RD_C2,		0,		AL	},
+{"vmidt.p", "?d5z",		0xf3830080, 0xffffff80, RD_C2,		0,		AL	},
+{"vmzero.p", "?d5z",		0xf3860080, 0xffffff80, RD_C2,		0,		AL	},
+{"vmone.p", "?d5z",		0xf3870080, 0xffffff80, RD_C2,		0,		AL	},
+{"vrot.p",  "?x1z,?s0y,?w",	0xf3a00080, 0xffe08080, RD_C2,		0,		AL	},
+{"vadd.s",  "?d0d,?s0s,?t0t",	0x60000000, 0xff808080, RD_C2,		0,		AL	},
+{"vsub.s",  "?d0d,?s0s,?t0t",	0x60800000, 0xff808080, RD_C2,		0,		AL	},
+{"vdiv.s",  "?x0d,?s0s,?t0t",	0x63800000, 0xff808080, RD_C2,		0,		AL	},
+{"vmul.s",  "?d0d,?s0s,?t0t",	0x64000000, 0xff808080, RD_C2,		0,		AL	},
+{"vcmp.s",  "?f2,?s0s,?t0t",	0x6c000000, 0xff8080f0, RD_C2,		0,		AL	},
+{"vcmp.s",  "?f1,?s0s",		0x6c000000, 0xffff80f0, RD_C2,		0,		AL	},
+{"vcmp.s",  "?f0",		0x6c000000, 0xfffffff0, RD_C2,		0,		AL	},
+{"vmin.s",  "?d0d,?s0s,?t0t",	0x6d000000, 0xff808080, RD_C2,		0,		AL	},
+{"vmax.s",  "?d0d,?s0s,?t0t",	0x6d800000, 0xff808080, RD_C2,		0,		AL	},
+{"vsgn.s",  "?d0d,?s0s",	0xd04a0000, 0xffff8080, RD_C2,		0,		AL	},
+{"vcst.s",  "?d0d,?a",		0xd0600000, 0xffe0ff80, RD_C2,		0,		AL	},
+{"vscmp.s", "?d0d,?s0s,?t0t",	0x6e800000, 0xff808080, RD_C2,		0,		AL	},
+{"vsge.s",  "?d0d,?s0s,?t0t",	0x6f000000, 0xff808080, RD_C2,		0,		AL	},
+{"vslt.s",  "?d0d,?s0s,?t0t",	0x6f800000, 0xff808080, RD_C2,		0,		AL	},
+{"vus2i.s", "?d1m,?s0y",	0xd03a0000, 0xffff8080, RD_C2,		0,		AL	},
+{"vs2i.s",  "?d1m,?s0y",	0xd03b0000, 0xffff8080, RD_C2,		0,		AL	},
+{"vmov.s",  "?d0d,?s0s",	0xd0000000, 0xffff8080, RD_C2,		0,		AL	},
+{"vabs.s",  "?d0d,?s0w",	0xd0010000, 0xffff8080, RD_C2,		0,		AL	},
+{"vneg.s",  "?d0d,?s0w",	0xd0020000, 0xffff8080, RD_C2,		0,		AL	},
+{"vsat0.s", "?d0z,?s0s",	0xd0040000, 0xffff8080, RD_C2,		0,		AL	},
+{"vsat1.s", "?d0z,?s0s",	0xd0050000, 0xffff8080, RD_C2,		0,		AL	},
+{"vzero.s", "?d0d",		0xd0060000, 0xffffff80, RD_C2,		0,		AL	},
+{"vone.s",  "?d0d",		0xd0070000, 0xffffff80, RD_C2,		0,		AL	},
+{"vrcp.s",  "?x0d,?s0s",	0xd0100000, 0xffff8080, RD_C2,		0,		AL	},
+{"vrsq.s",  "?x0d,?s0s",	0xd0110000, 0xffff8080, RD_C2,		0,		AL	},
+{"vsin.s",  "?x0d,?s0s",	0xd0120000, 0xffff8080, RD_C2,		0,		AL	},
+{"vcos.s",  "?x0d,?s0s",	0xd0130000, 0xffff8080, RD_C2,		0,		AL	},
+{"vexp2.s", "?x0d,?s0s",	0xd0140000, 0xffff8080, RD_C2,		0,		AL	},
+{"vlog2.s", "?x0d,?s0s",	0xd0150000, 0xffff8080, RD_C2,		0,		AL	},
+{"vsqrt.s", "?x0d,?s0s",	0xd0160000, 0xffff8080, RD_C2,		0,		AL	},
+{"vasin.s", "?x0d,?s0s",	0xd0170000, 0xffff8080, RD_C2,		0,		AL	},
+{"vnrcp.s", "?x0d,?s0y",	0xd0180000, 0xffff8080, RD_C2,		0,		AL	},
+{"vnsin.s", "?x0d,?s0y",	0xd01a0000, 0xffff8080, RD_C2,		0,		AL	},
+{"vrexp2.s", "?x0d,?s0y",	0xd01c0000, 0xffff8080, RD_C2,		0,		AL	},
+{"vrnds.s", "?s0y",		0xd0200000, 0xffff80ff, RD_C2,		0,		AL	},
+{"vrndi.s", "?d0d",		0xd0210000, 0xffffff80, RD_C2,		0,		AL	},
+{"vrndf1.s", "?d0d",		0xd0220000, 0xffffff80, RD_C2,		0,		AL	},
+{"vrndf2.s", "?d0d",		0xd0230000, 0xffffff80, RD_C2,		0,		AL	},
+{"vh2f.s",  "?d1d,?s0y",	0xd0330000, 0xffff8080, RD_C2,		0,		AL	},
+{"vsbz.s",  "?d0d,?s0s",	0xd0360000, 0xffff8080, RD_C2,		0,		AL	},
+{"vsbn.s",  "?d0d,?s0s,?t0t",	0x61000000, 0xff808080, RD_C2,		0,		AL	},
+{"vlgb.s",  "?d0d,?s0s",	0xd0370000, 0xffff8080, RD_C2,		0,		AL	},
+{"vocp.s",  "?d0d,?s0y",	0xd0440000, 0xffff8080, RD_C2,		0,		AL	},
+{"vsocp.s", "?d1z,?s0y",	0xd0450000, 0xffff8080, RD_C2,		0,		AL	},
+{"vf2in.s", "?d0m,?s0s,?b",	0xd2000000, 0xffe08080, RD_C2,		0,		AL	},
+{"vf2iz.s", "?d0m,?s0s,?b",	0xd2200000, 0xffe08080, RD_C2,		0,		AL	},
+{"vf2iu.s", "?d0m,?s0s,?b",	0xd2400000, 0xffe08080, RD_C2,		0,		AL	},
+{"vf2id.s", "?d0m,?s0s,?b",	0xd2600000, 0xffe08080, RD_C2,		0,		AL	},
+{"vi2f.s",  "?d0d,?s0w,?b",	0xd2800000, 0xffe08080, RD_C2,		0,		AL	},
+{"vcmov.s", "?d0d,?s0s,?e",	0,    (int) M_VCMOV_S,	INSN_MACRO,	0,		AL	},
+{"vcmovt.s", "?d0d,?s0s,?e",	0xd2a00000, 0xfff88080, RD_C2,		0,		AL	},
+{"vcmovf.s", "?d0d,?s0s,?e",	0xd2a80000, 0xfff88080, RD_C2,		0,		AL	},
+{"vwbn.s",  "?d0d,?s0s,?i",	0xd3000000, 0xff008080, RD_C2,		0,		AL	},
+{"vpfxs",   "?0,?1,?2,?3",	0xdc000000, 0xff000000, RD_C2,		0,		AL	},
+{"vpfxt",   "?0,?1,?2,?3",	0xdd000000, 0xff000000, RD_C2,		0,		AL	},
+{"vpfxd",   "?4,?5,?6,?7",	0xde000000, 0xff000000, RD_C2,		0,		AL	},
+{"viim.s",  "?t0d,j",		0xdf000000, 0xff800000, RD_C2,		0,		AL	},
+{"vfim.s",  "?t0d,?u",		0xdf800000, 0xff800000, RD_C2,		0,		AL	},
+{"vnop",    "",			0xffff0000, 0xffffffff, RD_C2,		0,		AL	},
+{"vflush",  "",			0xffff040d, 0xffffffff, RD_C2,		0,		AL	},
+{"vsync",   "",			0xffff0320, 0xffffffff, RD_C2,		0,		AL	},
+{"vsync",   "i",		0xffff0000, 0xffff0000, RD_C2,		0,		AL	},
+
 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
    instructions so they are here for the latters to take precedence.  */
 {"bc2f",    "p",	0x49000000, 0xffff0000,	CBD|RD_CC,		0,		I1	},
@@ -1198,6 +1505,36 @@
 {"mtc2",    "t,G,H",	0x48800000, 0xffe007f8,	COD|RD_t|WR_C2|WR_CC,	0,		I32	},
 {"mthc2",   "t,i",	0x48e00000, 0xffe00000,	COD|RD_t|WR_C2|WR_CC,	0,		I33	},
 
+/* Coprocessor 2 load/store operations overlap with the Allegrex VFPU
+   instructions so they are here for the latters to take precedence.  */
+/* COP1 ldc1 and sdc1 and COP3 ldc3 and sdc3 also overlap with the VFPU.  */
+{"ldc1",    "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	},
+{"ldc1",    "E,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	},
+{"ldc1",    "T,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		0,		I2	},
+{"ldc1",    "E,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		0,		I2	},
+{"l.d",     "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	}, /* ldc1 */
+{"l.d",     "T,o(b)",	0,    (int) M_L_DOB,	INSN_MACRO,		0,		I1	},
+{"l.d",     "T,A(b)",	0,    (int) M_L_DAB,	INSN_MACRO,		0,		I1	},
+{"ldc2",    "E,o(b)",	0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,		0,		I2	},
+{"ldc2",    "E,A(b)",	0,    (int) M_LDC2_AB,	INSN_MACRO,		0,		I2	},
+{"ldc3",    "E,o(b)",	0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,		0,		I2	},
+{"ldc3",    "E,A(b)",	0,    (int) M_LDC3_AB,	INSN_MACRO,		0,		I2	},
+{"lwc2",    "E,o(b)",	0xc8000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1	},
+{"lwc2",    "E,A(b)",	0,    (int) M_LWC2_AB,	INSN_MACRO,		0,		I1	},
+{"sdc1",    "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
+{"sdc1",    "E,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
+{"sdc1",    "T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		0,		I2	},
+{"sdc1",    "E,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		0,		I2	},
+{"s.d",     "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
+{"s.d",     "T,o(b)",	0,    (int) M_S_DOB,	INSN_MACRO,		0,		I1	},
+{"s.d",     "T,A(b)",	0,    (int) M_S_DAB,	INSN_MACRO,		0,		I1	},
+{"sdc2",    "E,o(b)",	0xf8000000, 0xfc000000, SM|RD_C2|RD_b,		0,		I2	},
+{"sdc2",    "E,A(b)",	0,    (int) M_SDC2_AB,	INSN_MACRO,		0,		I2	},
+{"sdc3",    "E,o(b)",	0xfc000000, 0xfc000000, SM|RD_C3|RD_b,		0,		I2	},
+{"sdc3",    "E,A(b)",	0,    (int) M_SDC3_AB,	INSN_MACRO,		0,		I2	},
+{"swc2",    "E,o(b)",	0xe8000000, 0xfc000000,	SM|RD_C2|RD_b,		0,		I1	},
+{"swc2",    "E,A(b)",	0,    (int) M_SWC2_AB,	INSN_MACRO,		0,		I1	},
+
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the
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